• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1170-1175
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• 2003

In this paper, the output power improvement of Push-Push FET DRO by adding the identical DR at the drain port as one used in the gate port, has been theoretically investigated. The investigation shows that the DR located between two microstrip lines locks the phase difference of two FET's outputs at 180 degree and improves the output power of Push-Push FET DRO. Since this effect can be used for correcting the impedance difference between two FETs output circuits and the electrical length error of the power combiner at the output circuit of Push-Push DRO, which may occur when fabricate the oscillator, the oscillator with an additional DR can be useful structure for fabricating oscillator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.21-28
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• 2008

In this paper, we suggest an analytical model that can derive the I-V characteristics in the saturation region of a short channel GaAs MESFET. Instead of the pinch-off concept that has been used in the conventional models we can derive the two-dimensional potential in the depletion region in order that the velocity saturation region cannot be pinched-off and the current continuity condition can be satisfied. Obtained expression for the velocity saturation length is expressed in terms of the total channel length, channel doping density, gate voltage, and drain voltage. Compared with the conventional channel length shortening models, the present model seems to be considerably accurate and more reasonable in explaining the Early effect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.9-15
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• 2004

We present a new unified analytical front surface potential model, which can accurately describe the transitions between the partially-depleted (PD) and the fully-depleted (FD) regimes with an analytical expression for the critical voltage V$_{c}$ delineating the PD and the FD region. It is valid in all regions of operation (from the sub -threshold to the strong inversion) and has the shorter calculation time than the iterative procedure approach. A charge sheet model based on the above explicit surface potential formulation is used to derive a single formula for the drain current valid in all regions of operation. Most of the secondary effects can be easily included in the charge sheet model and the model accurately reproduces various numerical and experimental results. No discontinuity in the derivative of the surface potential is found even though three types of smoothing functions are used. More importantly, the newly introduced parameters used in the smoothing functions do not strongly depend on the process parameter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.2
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• pp.8-13
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• 1999

In this paper, an analytical threshold voltage model is proposed by replacing the conventional GCA(Gradual Channel Approximation) with the assumption that a normal depletion layer width in the intrinsic region will vary quasi-linearly according to the channel direction. Derived threshold voltage expression is written as a function of the effective channel length, drain voltage, substrate bias voltage, substrate doping concentration, and the oxide thickness. Calculated results show almost similar trends with BSIM3v3's results in a satisfactory accuracy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.821-823
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 상하단 게이트 산화막 두께에 대한 드레인 유도 장벽 감소 현상에 대하여 분석하고자한다. 드레인 유도 장벽 감소 현상은 단채널 MOSFET에서 드레인전압에 의하여 소스측 전위장벽이 낮아지는 효과를 정량화하여 표현한다. 소스 측 전위장벽이 낮아지면 결국 문턱전압에 영향을 미치므로 드레인전압에 따른 문턱전압의 변화를 관찰할 것이다. 비대칭 이중게이트 MOSFET는 상단과 하단의 게이트 산화막 두께를 다르게 제작할 수 있는 특징이 있다. 그러므로 본 연구에서는 상단과 하단의 게이트 산화막 두께변화에 따른 드레인 유도 장벽 감소 현상을 포아송방정식의 해석학적 전위분포를 이용하여 분석하였다. 결과적으로 드레인 유도 장벽 감소 현상은 상하단 게이트 산화막 두께에 따라 큰 변화를 나타냈다. 또한 도핑농도에 따라 드레인유도장벽감소 현상이 큰 영향을 받고 있다는 것을 알 수 있었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.169-179
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• 1999

In this paper, a GaAs MESFET single-ended resistive mixer with high linearity and isolation is designed. The bias voltage of this mixer is applied only gate of GaAs MESFET to use the channel resistance. The LO is applied the gate and the RF is applied the drain through 7-pole hairpin bandpass filter to obtain the proper isolation thru LO-RF. The IF is extracted from the source with short circuit and lowpass filter. Using extracted equivalent circuits for LO and RF, conversion loss is calculated and compared with result of harmonic balance analysis. Measured conversion loss of this S-band down converter mixer is 8.2~10.5dB by considering the measured 3.0~3.4dB RF 7-pole hairpin bandpass filter loss and IP3in is 26.5dBm at Vg=-0.85~-1.0V in distortion performance.

• Journal of Drive and Control
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• v.20 no.4
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• pp.9-16
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• 2023

This paper analyzed a drainage tower used to drain water in flooded areas. Multi-body dynamics simulation was used to analyze the dynamic behavior of the drainage tower. Structural analysis, flexible-body dynamic analysis, and rigid body dynamic analysis were done to study the maximum Von-Mises stress of the drainage tower. The results showed that the maximum Von-Mises stress occurs at the turn table, and it decreases when the angle of the boom is increased. Also, the rate of the change of angle affects the maximum stress so that the maximum stress changes more when the angular velocity of the boom increases. Based on the rigid body dynamic analysis and the theoretical analysis results, the centrifugal force from the angular velocity makes the difference in the maximum stress at the turn table because of the difference in their direction. Consequently, it was concluded that the centrifugal force should be considered when designing construction machinerythat can rotate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.