• Journal of the Korea Society of Computer and Information
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• v.13 no.5
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• pp.27-35
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• 2008

The CTOC framework was implemented to efficiently perform analysis and optimization of the Java bytecode that is often being used lately. In order to analyze and optimize the bytecode from the CTOC, the eCFG was first generated. Due to the bytecode characteristics of difficult analysis, the existing bytecode was expanded to be suitable for control flow analysis. and the control flow graph was drawn. We called eCFG(extended Control Flow Graph). Furthermore, the eCFG was converted into the SSA Form for a static analysis. Many loops were found in the conversion program. The previous CTOC performed conversion directly into the SSA Form without processing the loops. However, processing the loops prior to the SSA Form conversion allows more efficient generation of the SSA Form. This paper examines the process of finding the loops prior to converting the eCFG into the SSA Form In order to efficiently process the loops, and exhibits the procedures for generating the loop tree.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5A
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• pp.514-520
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• 2004

In WDM networt a WDM buffer is one of essential elements for realizing all-optical packet switching system. In this paper, we propose and demonstrate a single loop type all-optical WDM buffer system. The proposed one consists of NOLM and feedback loop, and provides more than 40 turns buffering (more than 20${\mu}\textrm{s}$) for single input pulse (1550nm, width: 20㎱) before selected by control signal pulse (1553nm, width: 30㎱).

• Korean Chemical Engineering Research
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• v.58 no.3
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• pp.430-437
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• 2020

In this research, the anti-windup techniques for the cascade control system are newly developed. Cascade control system has an additional internal feedback control loop to reject disturbances better than the conventional control system. Remarkable difference between the conventional single-loop control system and the cascade control system is the interaction that the controller output saturation of the secondary control loop strongly affects the integral action of the primary control loop. In industry, local back calculation anti-windup method has been mainly used for each controller without considering the interaction between the two controllers. But it cannot eliminate the integral-windup of the primary controller originated from the saturation of the secondary controller output. To solve the problem, the two anti-windup techniques of the cascade conditional integration and the cascade back calculation are proposed in this research by extending the local anti-windup techniques for the single-loop control system to the cascade control system. Simulation confirmed that the proposed methods can effectively remove the integral windup of the primary controller caused by the saturation of the secondary controller output and show good control performances for various types of processes and controllers. If the reliability of the proposed methods is proved through the applications to real processes in the future, they would highly contribute to improving the control performances of the cascade control system in industry.

• Journal of Korea Society of Industrial Information Systems
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• v.25 no.4
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• pp.39-47
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• 2020

We propose a multi-access points transmit power control algorithm in consideration of the channel estimation error and the multi-rate service. In the real communication systems, the channel estimation at the receiver side is imperfect due to limited number of pilot symbol usage. Furthermore, the multi-rate service is supported. We theoretically prove the uniqueness and the convergence of the proposed algorithm in multi-rate service environment. The proposed algorithm composes of one inner loop part and one outer loop part. Simulation results show that 1) the inner loop algorithm guarantees convergence of the transmit power level and the multi-rate service, 2) the outer loop algorithm compensates for the channel estimation error.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.847-853
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• 2007

In this paper, a novel push-push voltage-controlled oscillator(VCO) using microstrip square open loop resonator and tunable negative resistance is presented. The microstrip square open loop resonator has the large coupling coefficient value, which makes a high Q value, and has reduced phase noise of VCO. The VCO with 1.8V power supply has phase noise of $-124.67{\sim}-122.67dBc/Hz\;@\;100 kHz$ in the tuning range, $5.744{\sim}5.859 GHz$. The FOM of this VCO is $-202.83{\sim}-201dBc/Hz\;@\;100 kHz$ in the same tuning range. When it has been compared with single-ended VCO using microstrip square open loop resonator, and push-push oscillator using microstrip line resonator, the reduced phase noise has been -8.51dB, and -33.67dB, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.96-101
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• 1998

많은 분야에서 널리 사용되고 있는 PID 제어기의 형태는 오차를 갖는 폐루프 시스템으로 구성되며, PID 제어기는 비례, 적분, 미분 제어기로 나누어진다. PID 제어기의 형태가 여러 가지로 제안되고 있지만 보다 중요한 것은 PID 제어기의 파라미터들을 어떻게 적절히 정하느냐 하는 파라미터 조정 문제이다. 실제로 산업 현장에 설치되어 있는 PID 제어기는 대부분 숙련된 기술자에 의해 수동 조작에 의한 시행 착오(trial and error) 법으로 동조되고 있다. 이 경우는 많은 노력과 시간이 소비되고, 외란(disturbance)이 첨가될 경우 적절히 동조된다는 보장도 없다. 본 논문에서는 이러한 문제를 해결하고자 신경회로망을 이용하여 PID 제어기의 파라미터를 동조하는 제어 방법을 제안하였다. 단일 뉴런으로 구성하여 구조가 간단하고, 학습에 의한 성능 개선이 가능하다. 오차 역전파(Error Back-Propagation) 알고리즘에 의하여 PID 파라미터가 되는 가중치를 자동 동조하는 방법이다. 제안한 방식의 유용성을 보이기 위해 DC 서보 모터와 비선형 시스템인 단일 관절 매니퓰레이터를 대상으로 시뮬레이션을 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1021-1026
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• 2005

In this paper, we present a novel predictive CDMA closed-loop power control (CLPC) method with a multi-step least squares (LS) linear predictor for time-varying fading channels. The proposed method effectively compensates multiple power control group delays and provides significant performance gains over nonpredictive CLPCs as well as conventional predictive CLPCs with one-step linear predictor.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2590-2592
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• 2000

본 논문에서는 TV 브라운관 유리용해로의 온도 제어를 위한 고전 고급 제어 (Conventional Advanced Control) 알고리듬을 제시한다. 용해로의 특성에 맞도록 중요한 입출력 변수를 선정한 후, 공정 실험을 통하여 얻어진 데이터를 바탕으로 입출력 변수들간의 초보적인 FOPDT (First Order Plus Dead Time) 모델들의 조합으로 용해로를 모델링하였다. 수립된 모델을 바탕으로 주요 입출력을 PI (Proportional - Integral) 형태의 cascade 및 단일 궤환 루프(Single feedback loop)들의 조합으로 제어기를 구성하였다. 제시된 알고리듬은 기존 용해로에 설치되어 있는 DCS를 이용하여 구현되었고, 일 150톤 생산 규모의 용해로에 성공적으로 실적용되었다.

• Journal of IKEEE
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• v.17 no.1
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• pp.16-21
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• 2013

Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.11
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• pp.2009-2014
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• 2017

A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.