• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.171-171
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• 2017

전산유체역학(CFD: Computational Fluid Dynamics)를 이용한 스마트팜 환경 내부의 정밀 제어 연구가 진행 중이다. 시계열 데이터의 난해한 동적 해석을 극복하기위해, 비선형 모델링 기법의 일종인 인공신경망을 이용하는 방안을 고려하였다. 선행 연구를 통하여 환경 데이터의 비선형 모델링을 위한 Tensorflow활용 방법이 하드웨어 가속 기능을 바탕으로 월등한 성능을 보임을 확인하였다. 그럼에도 오프라인 일괄(Offline batch)처리 방식의 한계가 있는 인공신경망 모델링 기법과 현장 보급이 불가능한 고성능 하드웨어 연산 장치에 대한 대안 마련이 필요하다고 판단되었다. CFD 해석을 위한 Solver로 SU2(http://su2.stanford.edu)를 이용하였다. 운영 체제 및 컴파일러는 1) Mac OS X Sierra 10.12.2 Apple LLVM version 8.0.0 (clang-800.0.38), 2) Windows 10 x64: Intel C++ Compiler version 16.0, update 2, 3) Linux (Ubuntu 16.04 x64): g++ 5.4.0, 4) Clustered Linux (Ubuntu 16.04 x32): MPICC 3.3.a2를 선정하였다. 4번째 개발환경인 병렬 시스템의 경우 하드웨어 가속는 OpenCL(https://www.khronos.org/opencl/) 엔진을 이용하고 저전력 ARM 프로세서의 일종인 옥타코어 Samsung Exynos5422 칩을 장착한 ODROID-XU4(Hardkernel, AnYang, Korea) SBC(Single Board Computer)를 32식 병렬 구성하였다. 분산 컴퓨팅을 위한 환경은 Gbit 로컬 네트워크 기반 NFS(Network File System)과 MPICH(http://www.mpich.org/)로 구성하였다. 공간 분해능을 계측 주기보다 작게 분할할 경우 발생하는 미지의 바운더리 정보를 정의하기 위하여 3차원 Kriging Spatial Interpolation Method를 실험적으로 적용하였다. 한편 병렬 시스템 구성이 불가능한 1,2,3번 환경의 경우 내부적으로 이미 존재하는 멀티코어를 활용하고자 OpenMP(http://www.openmp.org/) 라이브러리를 활용하였다. 64비트 병렬 8코어로 동작하는 1,2,3번 운영환경의 경우 32비트 병렬 128코어로 동작하는 환경에 비하여 근소하게 2배 내외로 연산 속도가 빨랐다. 실시간 CFD 수행을 위한 분산 컴퓨팅 기술이 프로세서의 속도 및 운영체제의 정보 분배 능력에 따라 결정된다고 판단할 수 있었다. 이를 검증하기 위하여 4번 개발환경에서 운영체제를 64비트로 개선하여 5번째 환경을 구성하여 검증하였다. 상반되는 결과로 64비트 72코어로 동작하는 분산 컴퓨팅 환경에서 단일 프로세서 기반 멀티 코어(1,2,3번) 환경보다 보다 2.5배 내외 연산속도 향상이 있었다. ARM 프로세서용 64비트 운영체제의 완성도가 낮은 시점에서 추후 성공적인 실시간 CFD 모델링을 위한 지속적인 검토가 필요하다.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.80-85
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• 2015

In this paper, we present, an indstrial RFID layered microstrip patch antenna is designed using an inset feed method in order to improve recognition rates in a long distance as tags are attached to metal object by improving a problem of feeding power in fabricating metal tags and reducing effects of metallic object. The inset feed shows a distinctive characteristic that has no separation between emitters and feed lines differing from a structure with the conventional inductive coupling feed. This structure makes possible to produce a type that presents a low antenna height and enables impedance coupling for tag chips. Although it shows a difficulty in the impedance coupling due to increases in the parasite capacitance between a ground plane and an emitter in an antenna according to decreases in the height of a tag antenna, it may become a merit in designing the tag antenna because the antenna impedance can be determined as an inductive manner if a shorted structure is used for feeding power. Therefore, in this paper the microstrip patch antenna is designed as a modified type and applies the inset feed in order to reduce effects of metallic objects where the antenna is be attached. Also, the antenna uses a multi-layer structure that includes a metal plate between radiator and ground instead of using a single layer.

• The Journal of the Korea Contents Association
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• v.15 no.9
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• pp.21-28
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• 2015

In the semi-conductor process, a simulation process is performed to detect defects by analyzing the behavior of the impurity through the physical quantity calculation of the inner element. In order to perform the simulation, Finite-Difference Time-Domain(FDTD) algorithm is used. The improvement of semiconductor which is composed of nanoscale elements, the size of simulation is getting bigger. Problems that a processor such as CPU or GPU cannot perform the simulation due to the massive size of matrix or a computer consist of multiple processors cannot handle a massive FDTD may come up. For those problems, studies are performed with parallel/distributed computing. However, in the past, only single type of processor was used. In GPU's case, it performs fast, but at the same time, it has limited memory. On the other hand, in CPU, it performs slower than that of GPU. To solve the problem, we implemented a computing model that can handle any FDTD simulation regardless of size on the cluster which consist of heterogeneous processors. We tested the simulation on processors using MPI libraries which is based on 'point to point' communication and verified that it operates correctly regardless of the number of node and type. Also, we analyzed the performance by measuring the total execution time and specific time for the simulation on each test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Korea Convergence Society
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• v.8 no.5
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• pp.161-167
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• 2017

We have fabricated and characterized $32{\times}32$ photonic quantum ring (PQR) laser arrays uniformly operable with $0.98{\mu}A$ per ring at room temperature. The typical threshold current, threshold current density, and threshold voltage are 20 mA, $0.068A/cm^2$, and 1.38 V. The top surface emitting PQR array contains GaAs multiquantum well active regions and exhibits uniform characteristics for a chip of $1.65{\times}1.65mm^2$. The peak power wavelength is $858.8{\pm}0.35nm$, the relative intensity is $0.3{\pm}0.2$, and the linewidth is $0.2{\pm}0.07nm$. We also report the wavelength division multiplexing system experiment using angle-dependent blue shift characteristics of this laser array. This photonic quantum ring laser has angle-dependent multiple-wavelength radial emission characteristics over about 10 nm tuning range generated from array devices. The array exhibits a free space detection as far as 6 m with a function of the distance.

• Korean Journal of Optics and Photonics
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• v.5 no.3
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• pp.423-430
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• 1994

We designed and fabricated the single mode fiber pigtailed DFB-LD module for 2.5 Gbps optical communication system. In the design of the DFB-LD module, we made the module divided into two parts of inner sub-module and outer 14-pin butterfly package and cylindrical shaped sub-module contain quasi confocal 2 lens system including optical isolator and electrical connection between these parts via hybrid substrate of bias T circuit. Laser welding was used to assemble the sub-module which requires accurate fixing between optical elements. The fabricated DFB-LD module showed optical coupling efficiency of 20% and - 3 dB small signal response of more than 2.6 GHz. We confirmed mechanical reliability of the module by temperature cycle test where the tested module exhibit optical power fluctuation of less than 10%. Finally we evaluated the performance of the fabricated DFB-LD module as light source of 2.5 Gbps optical communication system, sensitivity of - 30.2 dBm was obtained through 47 km optical fiber transmission under the criterion of $1\times10^{-10}$ BER and transmission penalties were 1.5 dB caused by extinction ratio and 1.0 dB caused by chromatic dispersion of normal single mode fiber. fiber.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.769-778
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• 2017

In this paper, a self-interference signal cancellation(SIC) circult for In-band Full-Duplex has been developed and tested in RF/analog region. By use of this SIC circuit, a FM two-way radio has been developed working at FRS(Family Radio Service) band. The two-way radio device is transmitting the FM modulated signal and demodulating the wanted FM signal at the same time. A circulator is used to enable a single antenna to transmit and receive simuultaenously. The receiver circuit needs to cancel out the self-interference signal due to the transmit signal. A vector modulator(VM) is used to control the phase and magnitude of the esitmated signal. And in-phase and quadrature correlators are used to figure out the optimal coefficients of the VM to remove the self-interference signal according to the change of channel environment. In this work, SA58646 has been used as the FM transceiver, and the system is tested with a frequency of 465 MHz and a bandwidth of 12.5 kHz FM signal. The output power is 17.2 dBm at the antenna port, and the self intererence signal level is measured -49.2 dBm at the receiver end. Therefore the SIC level is measured by 66.4 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.824-831
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• 2005

Past corporaion's network security system is single security solution, or mixed several ways, but there was inefficient system because doing not get into organic link But, constructed more strong security system by ESM enterance on. ESM uses way to integrate of each agent to manage easily various kinds security solution. That is, it is system that connect system of existent VPN, FireWall, IDS and so on configurationally depending on security policy and manage. ESM is security system that is developed more than existent security system. But, practical use of network and the development speed of technology being increasing with the mon faster speed, is heightening the level more as well as dysfunction of information crime and so on. Many improvements are required at ESM system, this research wished to make up for the weak-point in the ESM system about interior security. Studied on structure of security solution that is basis of security policy. VPN, Firewall, IDS's link that is main composition of existing security system analysis, reconstructed. And supplemented security of ESM system itself. Establish imaginary intrusion and comparative analysis access data that apply each Telnet Log analysys IDS existent ESM system and proposed ESM system comparative analysis. Confirm the importance of interior security and inspected security of proposed system.