• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.61-65
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• 2009

We produced noble surface structure of crystalline Si for solar cells by using preferential aqueous etching on crystallographic defects which were induced by grinding process. We analyzed the reflectance of textured surface according to surface topography resulting from various etchant concentrations and duration of etching process. The crystallographic defects and textured surface topography were investigated by using transmission electron microscopy and secondary electron microscopy, respectively. Also, the measurement of reflectance of textured surface utilizes spectrophotometer. The optimized texture surface exhibits improved result indicating reflectance of below ave. 1%. And it is cost-effective as well as taking short time within a few minutes.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.4
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• pp.141-147
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• 2018

Solar energy has attracted big attentions as one of clean and unlimited renewable energy. Solar energy is transformed to electrical energy by solar cells which are comprised of multi-silicon wafer or mono-silicon wafer. Monosilicon wafers are fabricated from the Czochralski method. In order to decrease fabrication cost, increasing a poly-silicon charge size in one quartz crucible has been developed very much. When we increase a charge size, the temperature control of a Czochralski equipment becomes more difficult due to a strong melt convection. In this study, we simulated a Czochralski equipment temperature at 20 inch and 24 inch in quartz crucible diameter and various charge sizes (90 kg, 120 kg, 150 kg, 200 kg, 250 kg). The simulated temperature profiles are compared with real temperature profiles and analyzed. It turns out that the simulated temperature profiles and real temperature profiles are in good agreement. We can use a simulated profile for the optimization of real temperature profile in the case of increasing charge sizes.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.305-310
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• 2013

In this paper, the pressure sensor usable in a high temperature, using a SDB(silicon-direct-bonding) wafer of Si/$SiO_2$/Si-sub structure was provided and studied the characteristic thereof. The pressure sensor produces a piezoresistor by using a single crystal silicon as a first layer of SDB wafer, to thus provide a prominent sensitivity, and dielectrically isolates the piezoresistor from a silicon substrate by using a silicon dioxide layer as a second layer thereof, to be thus usable even under the high temperature over $120^{\circ}C$ as a limited temperature of a general silicon sensor. The measured result for a pressure sensitivity of the pressure sensor has a characteristic of high sensitivity, and its tested result for an output of the sensor further has a very prominent linearity and hysteresis characteristic.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.27-36
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• 2006

We fabricated thermally evaporated 10 nm-Ni/(poly)Si, 10 nm-Ni/l nm-Ir/(poly)Si and 10 nm-Ni/l nm-Pt/(poly)Si films to investigate the thermal stability of nickel monosilicides at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides of 50 nm-thick were formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to examine sheet resistance. A scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An X-ray diffractometer and an Auger depth profiler were used for phase and composition analysis, respectively. Nickel silicides with platinum have no effect on widening the NiSi stabilization temperature region. Nickel silicides with iridium farmed on single crystal silicon showed a low resistance up to $1200^{\circ}C$ while the ones formed on polycrystalline silicon substrate showed low resistance up to $850^{\circ}C$. The grain boundary diffusion and agglomeration of silicides lowered the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.10
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• pp.3113-3125
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• 1996

The objective of this study is to develop novel method named mechanical and chemical machining technique, which is capable of producing three dimensional patterns of few micrometers in dimension on a silicon wafer without the use of a mask. The strategy is to impart mechanical energy along the path of the pattern to be fabricated on a single crystal silicon by way on introdusing frictional interaction under controlled conditions. Then, the surface is preferentially etched to reveal the areas that have been mechanically energized. Upon completion of the etching process, the three dimensional pattern is produced on the silicon surface. Experiments have been conducted to identify the optimal tool material, geometery, as well as fabrication condition. The new technique introduced in this paper is significantly simpler than the conventional method which require sophisticated equipment and much time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.81-81
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• 2009

반도체 산업의 중심 소재인 실리콘(Si)은 사용 목적과 환경에 따라 물성적 한계가 표출되기 시작했다. 그래서 각각의 목적에 맞는 재료의 개발이 필요하다는 것을 인식하게 되었다. SiC wafer는 큰 band gap energy와 고온 안정성, 캐리어의 높은 드리프트 속도 그리고 p-n 접합이 용이하다. 또한 소재 자체가 화학적으로 안정하고 $500\sim600^{\circ}C$에서 소자 제조 시 고온공정이 가능하며, 실리콘이나 GaAs에 비해 고출력을 낼 수 있는 재료이다. 반도체 소자로 이용하기 위한 wafer 가공 공정에 있어 물리적 힘에 의한 stress를 많이 받아 wafer가 휘는 현상이 생긴다. 반도체 소자의 기본이 되는 wafer가 휨 현상을 일으키면 wafer 위에 소자가 올라갈 경우 소자의 불균일성 때문에 반도체의 물성에 나쁜 영향을 미치게 된다. 그래서 반도체 소자의 기본이 되는 wafer의 휨 현상 개선이 중요하다. 본 연구에서는 산화로에서 Ar 분위기에서 압력 760torr, 온도 $1100^{\circ}C$ 부근에서의 조건으로 진행을 하여 wafer의 Flatness Tester(FT-900, NIDEK) 장비로 SORI, BOW, GBIR 값의 변화에 초점을 맞추었다. SiC 단결정을 sawing후 가공 전 wafer를 열처리하여 가공을 진행하는 것과 열처리 하지 않은 wafer의 SORI, BOW, GBIR 값 비교, 그리고 lapping, grinding, polishing 등의 가공 진행 중간 중간에 열처리를 하여 진행하는 것과 가공 진행 중간 중간에 열처리를 하지 않고 진행한 wafer의 SORI, BOW, GBIR 값의 비교를 통해 wafer의 휨 현상 개성에 관해 알아본다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.85-88
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• 2004

Mono-crystalline silicon(mono-Si) is both abundant in our environment and an excellent material for Si device applications. However, single crystalline silicon solar cell has been considered to be expensive for terrestrial applications. For that reason, the last few years have seen very rapid progress in the research and development activities of layer transfer(LT) processes. Thin film Si layers which can be detached from a reusable mono-Si wafers served as a substrate for epitaxial growth. The epitaxial films have a very high efficiency potential. LT technology is a promising approach to reduce fabrication cost with high efficiency at large scale since expensive Si substrate can be recycled. Low quality Si can be used as a substrate. Therefore, we propose one of the major technologies on fabricating thin film Si substrate using a LT. In this paper, we study the LT method using the electrochemical etching(ECE) and solid edge.

• Tribology and Lubricants
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• v.35 no.3
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• pp.176-182
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• 2019

The primary objective of this study is to treat a monocrystalline silicon (Si) wafer having a thickness of $279{\mu}m$ by employing the ultrasonic nanocrystal surface modification (UNSM) technology for improving the efficiency and service life of nano-electromechanical systems (NEMSs) and micro-electromechanical systems (MEMSs) by enhancing of wear and corrosion resistances. The wear and corrosion resistances of the Si wafer were systematically investigated before and after UNSM treatment, wherein abrasive, oxidative and spalling wear mechanisms were applied to the as-received and subsequently UNSM-treated Si wafer. Compared to the asreceived state, the wear and corrosion resistances of the UNSM-treated Si wafer are found to be enhanced by about 23% and 14%, respectively. The enhancement in wear and corrosion resistances after UNSM treatment may be attributed to grain size refinement (confirmed by Raman spectroscopy) and modified surface integrity. Furthermore, it is observed that the Raman intensity reduced significantly after UNSM treatment, whereas neither the Raman shift nor new phases were found on the surface of the UNSM-treated Si wafer. In addition, the friction coefficient values of the as-received and UNSM-treated Si wafers are found to be about 0.54 and 0.39, respectively. Hence, UNSM technology can be effectively incorporated as an alternative mechanical surface treatment for NEMSs and MEMSs comprising Si wafers.

• Journal of the Korean Electrochemical Society
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• v.4 no.1
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• pp.10-13
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• 2001

Effects of an anionic surfactant pentadecafluorooctanoic acid on the photoluminescence of porous silicon was investigated, which was prepared by photoelectrochemical etching at 4V of single crystalline n-type silicon (100) with the specific resistivity of $0.4\~0.8{\Omega}{\cdot}cm$. Photoluminescence shifted to shorter wavelength and its intensity decreased when the concentration of the surfactant increased. FT-IR and contact angle data supported the presence of the surfactant lying on the surface of porous silicon.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.1
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• pp.7-11
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• 2010

The reduction of optical losses in mono-crystalline silicon solar cell by surface texturing is a critical step to improve the overall cell efficiency. In this study, we have changed the sub-micrometer structure on the micrometer pyramidal structure by 2-step texturing. The Ag particles were coated on the micrometer pyramid surface in $AgNO_3$ solution, and then the etching with hydrogen fluoride and hydrogen peroxide created even smaller nano-pyramids in these pyramids. As a result, we observed that the changes of size and thickness of nano structure on pyramidal surface were determined by $AgNO_3$ concentration and etching time. Using 2-step texturing, the surface of wafers is etched to resemble the rough surface of a lotus leaf. Lotus surface can reduce average reflectance from 10% to below 3%. This reflectance is less than conventional textured wafer including anti-reflection coating.