• Journal of Internet of Things and Convergence
• /
• v.9 no.3
• /
• pp.81-86
• /
• 2023

SSD (solid state disk), which is flash memory-based storage device, has the advantages of high density and fast data processing. Therefore, it is being utilized as a storage device for high-capacity data storage systems that manage rapidly increasing big data. However, flash memory, a storage media, has a physical limitation that when the write/erase operation is repeated more than a certain number of times, the cells are worn out and can no longer be used. In this paper, we propose a method for converting defective multi-bit cells into single-bit cells to reduce the defect rate of flash memory and extend its lifetime. The proposed idea distinguishes the defects and treatment methods of multi-bit cells and single-bit cells, which have different physical characteristics but are treated as the same defect, and converts the expected defective multi-bit cells into single-bit cells to improve the defect rate and extend the overall lifetime. Finally, we demonstrate the effectiveness of our proposed idea by measuring the increased lifetime of SSD through simulations.

• Journal of Internet of Things and Convergence
• /
• v.9 no.4
• /
• pp.9-14
• /
• 2023

Recently, resource optimization research has been actively conducted in enterprises and data centers to manage the rapid growth of big data. In particular, thin provisioning, which allocates a large number of resources compared to fixedly allocated storage resources, has the effect of reducing initial costs, but as the number of resources actually used increases, the cost effectiveness decreases and the management cost for allocating resources increases. In this paper, we propose a technique that divides the physical blocks of flash memory into single-bit cells and multi-bit cells, formats them with a hybrid technique, and manages them by dividing frequently used hot data and infrequently used cold data. The proposed technique has the advantage that the physical and allocated resources are the same, such as thick provisioning, and can be used without additional cost increase, and the underutilized resources can be managed in multi-bit cell blocks, such as thin provisioning, which can allocate more resources than typical storage devices. Finally, we estimated the resource optimization effectiveness of the proposed technique through experiments based on simulations.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.7 s.361
• /
• pp.47-52
• /
• 2007

This paper analyzes the output signal-to-interference-plus-noise ratio (SINR) for a multiple-input-multiple-output (MIMO) multicarrier code division multiple access (MC-CDMA) system with minium mean square error receivers in multi-cell environments. A previous work in single cell environments is extended into analysis in multi-cell environments. The use of Haar unitary code matrix for asymptotic analysis causes other cell interferences expressed with a diagonal matrix haying different diagonal values. This paper shows that other cell interferences converge to an identity matrix whose gain is expressed by only other cell interference power in mean square sense and finds asymptotic deterministic SINRs for a given other cell interference. Under the assumption that the sum of lognormal fading components is distributed by other lognormal function, we show the comparison between theoretical performances and simulations from the view point of bit error rate and present average throughput performance according to the cell radius.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.12
• /
• pp.2331-2342
• /
• 2015

In this paper, we design non-linear transmitter and receiver using a uniform channel decomposition (UCD) to take account of inter-cell interference in multi-cell downlink systems. The designed UCD scheme brings forth the same SINR for all sub-channels in each cell. It provides great convenience to modulation/coding process and achieves the maximum diversity gain. The simulation results confirm that it exhibits a lower BER than the conventional method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.701-704
• /
• 2011

The reliability of a computer system largely depends on that of its memory systems, which are vulnerable to soft errors. Soft errors can be coped with a combination of an Error Detection & Correction circuit and scrubbing operation. Smaller geometries and lower voltage of advanced memories makes them more prone to suffer multibit soft errors. A memory structure against multibit soft errors and a suitable scrubbing scheme for it were proposed. This paper introduces a key issue for the scrubbing of the memories with protection against multibit soft errors and the result of the performance analysis from a reliability point of view.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2010.07a
• /
• pp.96-97
• /
• 2010

다중 홉 중계기술은 차세대 무선통신을 위한 핵심 기술로 최근 전 세계적으로 활발히 연구되고 있으며, 셀 용량 증대, 셀영역 확장, 음영지역 축소 등의 장점으로 인하여, IEEE 802.11s, 802.15.4, 802.16j 등의 표준화에의 반영을 위한 논의가 활발히 진행되고 있다. 본 논문에서는 간섭신호가 존재하지 않는 이상적 네트워크 환경을 고려한 기존 연구의 한계를 극복하기 위해, 다중 간섭신호가 존재하는 레일레이(Rayleigh) 페이딩 채널에서 이중 홉(dual-hop) 복호후재전송(DF : decode-and-forward) 중계시스템의 시스템 모델을 제안하고, 모의실험을 통하여 불능확률 및 4진 직교 진폭 변조(4-QAM)를 위한 평균비트오율 (average bit error rate) 성능을 살펴본다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.164-166
• /
• 2016

PRESENT/ARIA/AES의 3가지 블록 암호 알고리즘을 지원하는 암호 프로세서를 MPW(Multi-Project Wafer)칩으로 구현하였다. 설계된 블록 암호 칩은 PRmo(PRESENT with mode of operation) 코어, AR_AS(ARIA_AES) 코어, AES-16b 코어로 구성된다. PRmo는 80/128-비트 마스터키와, ECB, CBC, OFB, CTR의 4가지 운영모드를 지원한다. 128/256-비트 마스터키를 사용하는 AR_AS 코어는 서로 내부 구조가 유사한 ARIA와 AES를 통합하여 설계하였다. AES-16b는 128-비트 마스터키를 지원하고, 16-비트 datapath를 채택하여 저면적으로 구현하였다. 설계된 암호 프로세서를 FPGA검증을 통하여 정상 동작함을 확인하였고, 0.18um 표준 셀 라이브러리로 논리 합성한 결과, 100 KHz에서 52,000 GE로 구현이 되었으며, 최대 92 MHz에서 동작이 가능하다. 합성된 다중 암호 프로세서는 MPW 칩으로 제작될 예정이다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.9A
• /
• pp.722-728
• /
• 2005

In this paper, the reverse-link performance of synchronous DS-CDMA cellular networks is investigated in Rician multipath fading environments. The system's performance is evaluated in terms of the achievable average bit error rate BER) and the user capacities of two different network layouts, namely those of a uniform grid of hexagonal multiple cells and a single isolated cell. In the multiple-cell scenario, the impact of the other cells' interference on the attainable capacity of the synchronous DS-CDMA uplink is investigated. Upon comparing both networks to a conventional asynchronous CDMA system, we demonstrate an achievable user capacity gain of $25\%$ to $56\%$ for synchronous uplink transmissions over that of the corresponding asynchronous transmission scenario at BER = $10^{-3}$.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.7A
• /
• pp.964-972
• /
• 1999

In this paper, we proposed a simulation model to which apply the AAL 2 (AAL type 2) between BSC and MSC in the cellular mobile communication systems. We suggested the frame structure of processing the packets of short length and the scheme which multiplex to one or more ATM cell. Also, we analyzed the performance of the APR, transmission delay, and channel transmission efficiency used in the packetized voice traffic and the low bit-rate data traffic such as fax. From the simulation results, the maximum number of users are 47 users without using AAL 2 multiplexing, but the maximum number of users are 70 (Non-Overlapping scheme) users, 110 (Overlapping scheme) users, respectively. Thus, we knew that the Overlapping scheme is more efficient than the Non-Overlapping scheme. Finally, we showed that the optimum transmission buffer size is 4 ATM cells in the cellular communication systems with the bandwidth of 2 Mbps.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.11
• /
• pp.2093-2099
• /
• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.