• The KIPS Transactions:PartC
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• v.16C no.4
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• pp.417-422
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• 2009

Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.733-735
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• 2012

Real-Time Aperiodic Tasks Scheduling Using Synthetic Utilization on Multiprocessor Systems has a drawback in that if some tasks, even though they are completed and have no more execution times, are included in the current invocation set, their execution times and deadlines are added to the synthetic utilization. This may lead to a problem in which actually schedulable tasks are decided not to be schedulable. In this paper, we recognize the above mentioned problem and propose an improved synthetic utilization method that can be used to schedule aperiodic tasks more efficiently on multiprocessor systems.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.259-264
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• 2010

In case of scheduling tasks with shared resources in multiprocessor systems, Global Earliest Deadline First (GEDF) algorithm, equally applied Earliest Deadline First (EDF) which runs scheduling with deadline criterion, makes schedulability decline because GEDF typically does not have a specific process in order to handle tasks with shared resources. In this paper, we propose Earliest Deadline First with Partitioning (EDFP) for tasks with shared resources which partitions a task into two kinds of subtasks that include critical sections to access to shared resources, gives their own deadline respectively and manages them. As a result of simulations, EDFP shows better performance than GEDF for tasks with shared resources since system load goes up and the number of processor increases.

• The Magazine of the IEIE
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• v.18 no.7
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• pp.31-40
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• 1991

TICOM은 국내에서 독자적으로 설계, 개발한 수퍼미니급 컴퓨터 시스템이다. TICOM은 다중프로세서 구조에 UNIX를 기반으로 한 다중처리용 운영체제를 갖고 있다. 본 고는 한국전자통신연구소에서 개발한 행정전산망 주전산기 TICOM의 설계ROSUA, 시스템 구조와 특성을 살펴보고 시스템 성능에 대해 서술한다.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.541-556
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• 2005

The memory access latency of the system has been a primary factor of performance degradation in single-processor system and multi-processor system. The remote memory access latency takes a lot of overhead over the local memory access latency especially in the distributed shared-memory system. To resolve this problem, the multi-level cache architecture that contains a remote cache in the multi-processor system has been proposed. In this paper, we propose a new cache replacement policy that improves the performance of the multi-processor system with the remote cache. If the multi-level cache keeps the multi-level inclusion(MLI) property and uses the LRU(Least Recently Used) cache replacement policy, the LRU information of the higher-level cache(a processor cache) would be different with that of the lower-level cache(a remote cache). In this situation, the replacement of a remote cache line can induce the exchange of a processor cache line that is used by the processor. It is a main factor of performance degradation in a whole system. To alleviate this disadvantage of the LRU replacement polity, the new policy analyses tht processor's remote memory access pattern of each node and uses this information to reduce the number of invalidations of the useful cache line in the higher-level cache. The new replacement policy of the remote cache can improve the performance by $3.5\%$ in maximum and $2.5\%$ in average on SPLASH-2 benchmarks, compared to the general LRU cache replacement policy.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.06a
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• pp.85-88
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• 2003

본 논문에서는 다중 프로세서 시스템에서 부하를 재분배할 때 소요되는 통신비용을 줄이기 위한 알고리즘을 제안한다. 또한 시뮬레이션을 이용하여 제안된 알고리즘의 성능을 기존의 알고리즘과 비교한다. 제안하는 알고리즘에서는 되도록 많은 수의 링크가 부하 평형에 참여 할 수 있도록 한다. 이를 위하여 부하 이동량 계산시에 각 프로세서는 자신과 연결된 모든 링크를 이용하여 부하 평형을 시도한다. 그리고 한 번의 링크를 통해 이동되는 부하 량을 단위 량으로 제한시키는 대신에 반복적인 방법으로 부하 이동량을 계산한다. 시뮬레이션은 8$\times$8, 10$\times$10, 12$\times$12, 14$\times$14, 16$\times$16개의 프로세서를 갖는 메쉬 구조에서 실시하였다. 시뮬레이션 결과 기존의 알고리즘에 비하여 전체 부하 이동량은 약 30%, 부하 이동 시간은 약 70% 감소함을 보였다.

• Journal of Korea Multimedia Society
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• v.3 no.3
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• pp.309-319
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• 2000

The purpose of a parallel scheduling under a multiprocessor environment is to carry out the scheduling with the minimum synchronization overhead, and to perform load balance for a parallel application program. The processors calculate the chunk of iteration and are allocated to carry out the parallel iteration. At this time, it frequently accesses mutually exclusive global memory so that there are a lot of scheduling overhead and bottleneck imposed. And also, when the distribution of the parallel iteration in the allocated chunk to the processor is different, the different execution time of each chunk causes the load imbalance and badly affects the capability of the all scheduling. In the paper. we investigate the problems on the conventional algorithms in order to achieve the minimum scheduling overhead and load balance. we then present a new parallel loop scheduling algorithm, considering the locality of the data and processor affinity.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.113-115
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• 1998

다중프로세서 환경에서 타스크들을 할당해주는 중앙 프로세서를 두고 Laxity를 기반으로 긴급타스크를 선택하여 스케쥴링을 수행한다. 중앙프로세서는 프로세서들의 슬랙시간과 각 프로세서의 Local큐에 대기하고 있는 비주기적 타스크의 총 수행시간 등의 상태정보를 수집 분석하여, 타스크의 실행시간에 가장 적합한 프로세서를 선xor하여 할당한다. 또한 타스크 특성에 따라 주기적 타스크와 비주기적 타스크로 나누고 주지적 타스크는 마감시간을 지키는 범위 내에서 최대한 수행시간을 연기 시켰다. 시뮬레이션 결과 Overload(마감시간을 지키지 못하는 타스크)수의 감소와 빠른 응답시간을 제공함을 알 수 있었다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.68-77
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• 2003

The Least-Laxity First(or LLF) scheduling algorithm assigns the highest priority to a task with the least laxity, and has been proved to be optimal for a uni-processor and sub-optimal for a multi-processor. However, this algorithm Is Impractical to implement because laxity tie results in the frequent context switches among tasks. In this paper, a Modified Least-Laxity First on Multiprocessor(or MLLF/MP) scheduling algorithm is proposed to solve this problem, i.e., laxity tie results in the excessive scheduling overheads. The MLLF/MP is based on the LLF, but allows the laxity inversion. MLLF/MP continues executing the current running task as far as other tasks do not miss their deadlines. Consequently, it avoids the frequent context switches. We prove that the MLLF/MP is also sub-optimal in multiprocessor systems. By simulation results, we show that the MLLF/MP has less scheduling overheads than LLF.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1025-1031
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• 2007

This paper proposes an area-efficient pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving antennas. Since the MIMO-OFDM system transmits multiple data streams, the complexity for the MIMO-OFDM system with a single-channel FFT processor increases linearly with the increase of the number of transmit channels. The proposed FFT processor is based on multi-channel structure, and therefore it can efficiently support multiple data streams. With the mixed radix algorithm, the number of non-trivial multiplications of the proposed FFT processor is decreased. The proposed FFT processor is synthesized with CMOS $0.18{\mu}m$ process and reduces the logic gates by 25% over a 4-channel Radix-4 multi-path delay commutator (R4MDC) FFT processor. Since the MIMO-OFDM FFT processor is one of the largest modules in the systems, the proposed FFT processor will be a vast contribution improvement to the low complexity design of MIMO-OFDM systems.