• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.3
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• pp.6-12
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• 2011

Electric vehicles and robots are real-time distributed control systems composed of multiple drive subsystems using micro controller units. Each control subsystem should be modular, compact, power saving, interoperable and fault tolerable in order to be incorporated into the networked real-time distributed control system. Under the networked real-time distributed control the synchronization problem can be occurred to the position and orientation tracking control due to the load variance, mismatch and time delay between the multiple drive subsystems. This paper suggests two types of position synchronization control of the single link manipulators. One of them is composed of cross controller, Kalman filter and disturbance observer, and the other uses the generation of target trajectories to minimize the gradient vector of the scalar function which is composed of the sum of square errors between the reference input vector and the output vectors. The availability of the proposed control schemes is shown through the control experiments.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.473-486
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• 2004

NUMA systems have remote access caches(RAC) in each local node to reduce the overhead for repeated remote memory accesses. By this RAC, memory latency and network traffic can be reduced and the performance of the multiprocessor system can be improved. Until now, several cache replacement policies have been proposed in recent years, and there also is cache replacement policy for multiprocessor systems. In this paper, we propose a cache replacement policy which is based on cache line coherence information. In this policy, the cache line that does not have an ownership is replaced first with respect to cache line that has an ownership. Like this way, the overhead to transfer ownership is avoided and the memory latency can be decreased. We also propose “Keeping-Ownership replacement policy with MRU (KOM)” and “Keeping-Ownership replacement policy with Reference Bit(KORB)” to reduce the frequent replacement penalty of the ownership-lacking cache line. We compare and analyze these with LRU and Pseudo LRU(PLRU). The simulation shows that KOM outperforms the PLRU by 25%, and KORB outperforms the PLRU by 13%. Although the hardware cost of KOM is very small, the performance of KOM is nearly equal to that of the LRU.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.519-524
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• 2002

In this paper we study the qualify of sequential coverage analysis under a scenario of distributed stochastic simulation known as MRIP(Multiple Replications In Parallel) in terms of the confidence intervals of coverage and the speedup. The estimator based in the F-distribution was applied to the sequential coverage analysis of steady-state means. in simulations of the $M/M/1/{\infty},\;M/D/I/{\infty}\;and\;M/H_{2}/1/{\infty}$ queueing systems on a single processor and multiple processors. By using multiple processors under the MRIP scenario, the time for collecting many replications needed in sequential coverage analysis is reduced. One can also easily collect more replications by executing it in distributed computers or clusters linked by a local area network.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.149-159
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• 2000

In this paper, we propose a new class of MIN (Multistage Interconnection Network) called SCMIN(ShortCut MIN) which can form a cheap and efficient packet switching interconnection network. SCMIN satisfies full access capability(FAC) and has multiple redundant paths between processor-memory pairs even though SCMIN is constructed with 2.5N-4 SEs which is far fewer SEs than that of MINs. SCMIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. Therefore, SCMIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.169-174
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• 1986

This thesis investigates the scanning time ; one of the most important performance index of Programmable Controller(PC). The multiprocessor architecture of the large PC considered in this thesis are classified as architecture 1 and architecture 2 by the bus control methods. The queuing model of each architecture is developed. Form the analysis it is observed that in the case of the number of processors less than 3 the best architecture of the large PC is the architecture 2 and in the case of the number of processors greater than 2 the best architecture of the large PC is the architecture 1.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.2
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• pp.164-175
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• 1999

본 논문은 종속적인 작업들의 시간 제한요건 검증에 관한 연구이다. 종속적인 작업들은 임의의 시간 제한요건과 가변의 수행시간을 가지며 우선순위 구동 방식에 따라 동적으로 다중프로세서 시스템에 스케줄된다. 본 논문에서는 종속적인 작업들이 예측 가능한 방법으로 수행될 수 있는 조건들을 제시한다. 즉, 모든 작업들이 각각 가장 긴 수행시간을 갖는 경우를 시뮬레이션했을 때의 종료시각이 모든 작업들의 수행종료 시각을 바운드하는 경우들을 제시하고 증명한다. 또한, 일반적인 경우에 모든 작업들의 가장 늦은 수행종료시각을 바운드할 수 있는 알고리즘들을 제시한다.

• The KIPS Transactions:PartD
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• v.15D no.3
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• pp.355-360
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• 2008

The complicated embedded system for multi-tasking requires RTOS(real-time operating system). It uses the optimal OS and processor to each embedded system on the heterogeneous development environment. This paper is proposed to use UML profile of OS API and Processor Configuration, instead of cross-compiling for developing the heterogeneous embedded system. This reduces the development time and cost through generating the automatic source code with the profile information of each embedded system. We generate and port the code after modeling the two heterogeneous real time operating systems (brickOS and uC/OS-II) and the processors (Hitachi H8 and Intel PXA255) with our proposed profile of the heterogeneous embedded system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.175-182
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• 2011

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.53-62
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• 2010

Recently, various industrial embedded systems including vehicles controlled electronically are evolving to distributed multi-micro controller system. Accordingly, there is a need for standard CAN(Controller Area Network) protocol that ensures high stability and reliability of communication and is simple to construct object-oriented system with high control efficiency. CAN communication interface used general-purpose processor doesn't have many limitations in various application development because of fixed hardware architecture. This paper design and implement a CAN communication interface system based on FPGA. It is verified function and performance of system through monitoring communication with existing AT90CAN128 controller. Implemented CAN communication interface can be reused in development of application systems based on FPGA. And it provides low-cost, small-size and low-power design advantages.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.44-51
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• 1999

This paper presents a massively parallel computational model for the efficient integration of speech and natural language understanding. The phoneme model is based on continuous Hidden Markov Model with context dependent phonemes, and the language model is based on a knowledge base approach. To construct the knowledge base, we adopt a hierarchically-structured semantic network and a memory-based parsing technique that employs parallel marker-passing as an inference mechanism. Our parallel speech recognition algorithm is implemented in a multi-Transputer system using distributed-memory MIMD multiprocessors. Experimental results show that the parallel speech recognition system performs better in recognition accuracy than a word network-based speech recognition system. The recognition accuracy is further improved by applying code-phoneme statistics. Besides, speedup experiments demonstrate the possibility of constructing a realtime parallel speech recognition system.