• Journal of KIISE:Computing Practices and Letters
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• v.5 no.6
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• pp.708-718
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• 1999

본 논문에서 제안하는 시스템은 일반적인 병렬 시스템의 하드웨어 구조에서, 다중 스레드 계산 모델을 이용하여 객체 지향 프로그래밍 환경을 구현한 시스템이다. 제안하는 시스템을 효과적으로 구현하기 위하여 컴파일러와 실행 시간 시스템의 측면에서 여러 가지 기법을 제시한다. 컴파일러의 측면에서는 멤버 변수의 접근 분석, 메소드의 병렬성 분석 기법을 제시하고, 실행 시간 시스템에서는 실시간 스레드/메시지 결합, 프레임 공유 기법을 제시한다. 본 논문에서 제안된 프로그래밍 환경은, MPI 메시지 인터페이스를 이용하여 구현하였으며, 벤치마크 프로그램을 실행함으로써 성능 분석을 하였다. 분석의 결과는 실행시간 시스템의 여러 가지 기법들이 성능 향상에 많은 효과가 있음을 보여주며, 이러한 결과는 일반적인 병렬 시스템에서도 적용 가능하다.Abstract In this paper, we suggest an object-oriented programming environment with multithreaded computation model on general parallel processing systems. We developed many methods for our environment to be efficient : in compiler, the analysis of member variable and method parallelism, and in runtime system, thread/message merging and frame sharing. The programming environment is implemented with MPI message interface, and its performance is analyzed with executing benchmark programs. The results show that the developed methods have influence on performance improvement, and this improvement can be applied to general parallel processing systems.

• Journal of Information Management
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• v.29 no.3
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• pp.1-26
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• 1998

The loop is a fundamental for the parallelism exploiting as it has a large portion of execution time for sequential Java program on the parallel machine. This paper proposes the method of exploiting the implicit parallelism through the analysis of data dependence in the existing Java programming language having a single loop structure. The parallel code generation method through the restructuring compiler and the translation method of Java source program into multithread statement, which is supported in the level of the Java programming language, are also proposed here. The performance test of the program translated into the thread statement is conducted using the trip count of loop and the thread count as parameters. The restructuring compiler makes it possible for users to reduce overhead and exploit parallelism efficiently in the Java programming.

• The Transactions of the Korea Information Processing Society
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• v.7 no.3
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• pp.962-970
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• 2000

Multithreading is attractive in that it can tolerate memory latency and synchronization by effectively overlapping communication with computation. While several compiler techniques have been developed to produce multithreaded codes from functional languages programs, there still remains a lot of works to implement loops effectively. Executing lops in a style of multithreading usually causes some overheads, which can reduce severely the effect of multirheading. This paper suggests several methods in terms of architectures or compilers which can optimize loop execution by multithreading. We then simulate and analyze them for the matrix multiplication program.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.974-984
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• 1995

This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.

• The Journal of Korean Association of Computer Education
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• v.17 no.1
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• pp.107-115
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• 2014

This paper evaluates and analyzes the performance of TILE-Gx36(Gx36), a many-core processor. The PARSEC parallel benchmark suite was used to measure the performance, and Core i7 (i7) and Atom are used for the performance comparison. When experimented with the maximum number of threads that can be executed concurrently on each machine, Gx36 showed a 2.73${\times}$ inferior performance to Core i7 and a 1.93${\times}$ superior performance to Atom. Gx36 has the largest Last Level Cache(LLC) among the compared processors. Nevertheless, it reported the biggest number of LLC misses, which, we strongly believe, is the major culprit for lower performance than expected. Our study suggests that the DDC employed in Gx36 is not a favorable cache structure for the general-purpose high-performance computing. The actual measurement with off-the-shelf machine provides non-biased data for polishing the future many-core architecture.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.377-383
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• 1997

This paper presents the design and the implemenration of a Mutiuser Multimedia Confernce System for synchronous groupwork.The infrastructure of this system is a hybrid srchiercture of centralized and replicated archietctures,that is to maintain sharde information cinsistently and to reduce the overhead of network traffic to the central part.The communication control of data for groupwerk managrment is centralized to the virtual node and the communication control of real data such as audio,video,text is replicated.In order ot provide a realtime audio and video processing,this system uses synamic queues and multithreads.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.6
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• pp.505-513
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• 2021

We propose an autonomous mission management software design and verification technique for unmanned aerial vehicles to autonomously mitigate dynamic situation changes occurred in the inside and outside of an aircraft in compliance with the mitigation priority order. The proposed autonomous mission management software is designed in a modular architecture that consists of concurrently executing multiple threads. To verify it, we suggest three verification steps: 1) software integration by checking the expected request/response messages between the threads for all possible dynamic situation changes; 2) integration test to verify the software functionality; 3) performance test to verify the quantitative software performance. Especially, the software integration test environment is built and utilized to carry out the integration and performance tests.

• Journal of the HCI Society of Korea
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• v.14 no.2
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• pp.31-39
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• 2019

This research examined the changes that fast-growing voice-based devices would bring in the media multitasking environment. Based on the theoretical background that information processing efficiency improves when performing multiple tasks requiring different resource structures at the same time, we conducted an experiment where participants searched for information with voice-based or screen-based devices while performing an additional visual task. Results showed that both task performance environment and interface modality had significant main effects on cognitive load. The overall cognitive load level was higher in the voice interface group, but the difference in cognitive load between the two groups decreased in a multitasking environment where the additional visual resources was required. The visual task performance was significantly higher when using the voice interface than the screen interface. Our findings suggest that voice interfaces offered advantages in the cognitive load and task performance by distributing two tasks to the auditory and visual channels. The results of this study imply that voice-based devices have the potential to facilitate efficient information processing in the screen-centric environment where visual resources collide. We provided theoretical evidence of resource distribution using multiple resource theory and tried to identify the advantages of the voice interface more specifically based on the threaded cognition model.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.3
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• pp.69-75
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• 2011

In this paper, we propose an anycast event driven synchronization mechanism to reduce power overheads. Our proposed mechanism can reduce unnecessary polling operations on SHI(Snoop Hit Invalidate) or SHR(Snoop Hit Read) states. It prevents waisting bandwidth and reduces power overheads on polling operation. Also it decreases transition power of state change compared to broadcast model. Simulation results indicated that the proposed architecture had about 15.3% of power decrease compared to spin-lock model and about 4.7% of power decrease compared to broadcast model. Overall results indicated that proposed synchronization mechanism could increase power efficiency of multi-core system by reducing power overheads.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.76-86
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• 1997

Many information retrieval systems have a simple process structure that a client process for a user is mapped to a server process for information retrieval. That is, when using information retrieval systems, each user is allocated a big process that consists of user interfaces, retrieval automatic indexing systems and storage systems. Therefor when many users use the information retrieval systems, it might be difficult to use the information retrieval systems. This is because the system overhead is increased as enormously much as users cannot use them. In this paper, we propose a new process structure for constructing efficient information retrieval systems that solves the problem resulting from he process structure. The proposed process structure contributes to the whole operational performance improvement of information retrieval systems and the efficientnt use of computer system resources. It is constructed based on a multi-threading scheme and a transaction processing monitor.