• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.3-6
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• 2000

DSL 서비스에서 보다 고속의 데이터 전송을 위하여 심볼률을 확장하면 부분적으로 대역이 겹치는 반향신호가 발생한다. 이에 기존의 다상 반항제거기를 적용하면 높은 심볼률로 인하여 엄청난 연산량을 필요로 한다. 본 논문에서는 부분적으로 대역이 겹치는 반향신호를 기존의 절반이하의 연산량으로 제거하는 새로운 반향제거기 구조를 제안한다. 이는 다중률 필터링을 통하여 신호처리의 속도를 낮춘 것으로서, 뛰어난 연산절감과 아울러 기존의 반향제거기와 방불한 성능을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.4
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• pp.170-178
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• 1984

For the reduction of the 12-channel TDM/FDM translation time the 14-point fast DCT algorithm is used and the polyphase network which translates the prototype filter into the channel filters required in each channel is designed. For the prototype filter the degree of the numerator is 168 and the coefficients have symmetry values, the degree of the numerator is 6. Such a prototype filter is consistant with the CCITT requirements. In this case the required multiplication rate is CCITT requirements. In this case the required multiplication rate is $0.12267{\times}10^2$ multiplications/sec. channel and reduces to about 15-40% of the rate required in the exising systems. The proposed 12-channel TDM/FDM translation system is simulated using a demodulation system with a computer (PRIME 750) and the results show that the proposed conversion method is valid.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.5
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• pp.475-481
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• 2021

The on-board processor of satellite Synthetic Aperture Radar(SAR) digitizes the back-scattered echoes and transmits them to the ground. As satellite SAR image of various operating conditions including broadband and high resolution is required, an enormous amount of SAR data is generated. Decimation filter is used for data compression to improve the transmission efficiency of these data. Decimation filter is implemented with the FIR(Finite Impulse Response) filter and here, the decimation ratio and tap length are constrained by resource requirements of FPGA used for implementation. This paper suggests to use a non-integer ratio decimation filter in order to optimize the data transmission efficiency. Also, it proposes a filter design method that remarkably reduces the resource constraints of the FPGA in-use via applying a polyphase filter structure. The required resources for implementing the proposed filter is analysed in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.209-216
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• 2009

The repeater for wireless broadband internet (Wibro) system using OFDM demands the short processing delay to eliminate inter-symbol interference resulted from the time delay greater than the guard time. Towards this, the total system delay of repeater is expected to be minimized as possible as it can without distorting signal quality. In general, the FIR-type of filter is commonly deployed as a channelization filter, but due to its large amount of coefficients for producing prerequisite filter response the excessive large time delay occurs. To withstand this problem, the paper proposes the method for designing IIR filter whose response almost identical to that of the original filter. Moreover, in order to linearize the phase response of the designed IIR filter, this paper also introduce the way of designing the all-pass filter to be cascaded works for linearizing phase response of the channelization as well as the de-channelization filter. To achieve the further improvement in linearization of the phase response and reduction of the overall complexity, this paper tries to transform the integrated IIR filter group into the structure in polyphase style. The computer simulation verifies that the integrated IIR filter group designed in this paper reveals the relatively short processing delay without harming the acceptible signal quality.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.329-331
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• 2008

기존의 발전용 연료전지 PCS 는 주로 DC-DC 컨버터 없이 인버터만 있는 방식이거나 3상의 DC-DC 컨버터에 인버터를 사용하는 방식이다. 본 논문에서는 발전용 연료전지 PCS의 부피저감과 고효율을 위한 DC-DC 컨버터의 최적 설계를 제안한다. 제안하는 DC-DC 컨버터는 DCM에 의한 소프트 스위칭으로 스위칭 주파수를 증가시킴과 동시에 상수를 증가시키는 방식으로 다상의 인터리빙으로 인해 필터 부피가 작아져 전체 PCS 효율을 높게 유지하면서 부피를 저감할 수 있다. 본 논문에서 PCS의 이론적 효율계산을 통해 DC-DC 컨버터의 최적 상수를 선정하였다.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2610-2612
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• 2004

The polyphase filter-based orthogonal frequency division multiplexing (PF-OFDM) is proposed in [1]. It provides more efficient data transmission mechanism than the classical OFDM method. However, the channel estimation mechanism in the classical OFDM system such as the cyclic prefix can not be applied straightforwardly, since the received signal contains unpredictable terms. Therefore, the PF-OFDM system requires a complicated channel estimation scheme when it works on the multipath fading communication channel. In this paper, we proposed a pilot-symbol aided channel estimation algorithm suitable for the PF-OFDM system which efficiently deals with the unpredictable terms and verified its performance through a series of computer simulations.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.7
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• pp.641-647
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• 2015

In this paper, Analyzed the multi-channel signal processing algorithms for digital-transponder. To analyze suitable multi-channel signal processing algorithms, compare algorithms about four criteria. Four criteria are as follows, perfect reconstruction, interference rejection, resource usage and power consumption. Analysis for each algorithm in accordance with these four criteria. then propose the multi-channel signal processing algorithms for digital satellite communication system.