• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.14 no.4
• /
• pp.49-59
• /
• 2004

Boolean function synthesize problem is to find a boolean expression with in/outputs of original function. This problem can be modeled into a 0-1 integer programming. In this paper, we find a boolean expressions of S-boxes of DES for an example, whose algebraic structure has been unknown for many years. The results of this paper can be used for efficient hardware implementation of a function and cryptanalysis using algebraic structure of a block cipher.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.12
• /
• pp.3688-3693
• /
• 2009

In this paper the design methode of a separated composition state machine based on the compositive map with connecting two chaotic maps together - sawtooth map $S_2(x)$ and tent map $T_2(x)$ and the result of that is proposed. this paper gives a graph of the chaotic states generated by the composition state machine using the compositive logic of two different chaotic maps - sawtooth map and tent map and also shows that the period of pseudo-random states has the length according to the precision of the discreet truth table.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.4
• /
• pp.1-6
• /
• 2020

This paper proposes the design of an advanced S-Box for calculating multiplicative inverse in AES encryption process. In this approach, advanced S-box module is first designed based on composite field, and then the performance evaluation is performed for S-box with multi-stage pipelining architecture. In the proposed S-Box architecture, each module for multiplicative inverse is constructed using combinational logic for realizing both small-area and high-speed. Through logic synthesis result, the designed 3-stage pipelined S-Box shows speed improvement of about 28% compared to the conventional method. The proposed advanced AES S-Box is performed modelling at the mixed level using Verilog-HDL, and logic synthesis is also performed on Spartan 3s1500l FPGA using Xilinx ISE 14.7 tool.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.2
• /
• pp.445-453
• /
• 2005

The design process of a relational database system consists of requirement analysis, conceptual design using ER diagram, logical design, and physical design. In logical design process, the conceptual schema is transformed to relational schema, and relational schema is normalized. This traditional design process is hard to applied in real database design process, since there is an ambiguity in conceptual design process. In this paper, we suggest a new design process, which provides more structural design steps by removing the conceptual design process. In new approach, we produce the data flow diagram by the structural methodology. From the attributes in the data store of data flow diagram, we construct relational table schema, and we normalize relational schema. Finally we produced table relationship diagram in order to figure out relationships between tables.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.12 no.4
• /
• pp.21-27
• /
• 1975

In this paper, a procedure for deriving of multiple fault detection test sets is presented for fan-out reconvergent combinational logic networks. A fan-out network is decomposed into a set of fan-out free subnetworks by breaking the internal fan-out points, and the minimal detecting test sets for each subnetwork are found separately. And then, the compatible tests amonng each test set are combined maximally into composite tests to generate primary input binary vectors. The technique for generating minimal test experiments which cover all the possible faults is illustrated in detail by examples.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.1
• /
• pp.57-63
• /
• 1994

The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2002.05d
• /
• pp.741-746
• /
• 2002

본 논문에서는 학습자 스스로가 학습 능력을 조절하고 학습 내용과 시험 평가를 객관적으로 판단할 있는 자기 주도적 학습 내용 및 시험 평가 방법을 제안하였다. 제안된 자기 주도적 학습 내용 및 시험평가 방법은 삼각형 타입의 소속 함수와 퍼지 논리를 이용하여 학습 능력과 시험 능력의 소속도를 계산하고 각각에 대해 퍼지 등급도를 부여하였다. 학습 능력의 소속도와 시험 능력의 소속도에 대해서 퍼지 관계의 연산 및 합성에 의해 최종 소속도를 계산하고 퍼지 등급도를 결정하여 학습자가 학습 능력의 소속도와 시험 능력의 소속도 및 최종 퍼지 등급도를 분석하여 스스로 학습을 조정할 수 있도록 하였다. 그리고 제안된 연구 내용을 정보 검색사 필기 과목에 적용하여 구현하였다.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.12
• /
• pp.43-53
• /
• 1997

In this paper, the optimal synthesis algorithm of multiple-valued logic circuits using universal logic modules (ULM) U$_{f}$ based on 3-variable ternary reed-muller expansions is presented. We check the degree of each varable for the coefficients of reed-muller expansions and determine the order of optimal control input variables that minimize the number of ULM U$_{f}$ modules. The order of optimal control input variables is utilized the realization of multiple-valued logic circuits to be constructed by ULM U$_{f}$ modules based on reed-muller expansions using the circuit cost matrix. This algorithm is performed only unit time in order to search for the optimal control input variables. Also, this algorithm is able to be programmed by computer and the run time on programming is O(p$^{n}$ ).

• Proceedings of the Korean Information Science Society Conference
• /
• 2005.07a
• /
• pp.460-462
• /
• 2005

본 논문은 통신 시스템에서 오류 검출을 위해 널리 사용되고 있는 Cyclic Redundancy Check (CRC)회로의 병렬 구현을 위한 최적화 알고리즘을 제시한다. 논리 단을 최소로 하면서 가능한 않은 공유 텀을 찾아 매핑 함으로써 속도 및 게이트 수를 줄인다. 본 논문에서는 이더넷의 32비트 CRC를 병렬로 구현하여 성능평가를 하였다. FPGA 및 표준 셀 라이브러리를 이용하여 합성하였으며, 기존의 방식에 비해 속도와 면적 모두 향상되었음을 보여준다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.7
• /
• pp.422-430
• /
• 2002

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Since the maximum number of the LUT's required in the same time determines the size of the chip used in the synthesis, it needs to be minimized, if possible. Many previous work use their own approaches, which are very similar to either scheduling method in high level synthesis or multi-way circuit partitioning method, to solve the problem. In this paper, we propose a method which estimates the lower bound on the number of LUT's without performing any actual synthesis. The estimated lower bounds help to evaluate the results of the previous work. If the estimated lower bound on the number of LUT's exactly matches the number of LUT's of the result from the previous work, the result must be optimal. In contrast, if they do not match, the following two cases are expected : the more exact lower bound may exist, or we might find the new synthesis result better than the result from the previous work. Experimental results show that our lower bound estimation method is very accurate. In almost al] cases experimented, the estimated lower bounds on the number of LUT's exactly match those of the previous synthesis results respectively, implying that the best results from the previous work are optimal as well as our method predicted the exact lower bound for those examples.