• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.

• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.242-245
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• 1985

논리회로의 합성이란 minimize된 Boolean Expression을 실재로 존재라는 TTL IC로 Implement시키는 과정을 말한다. 즉, IC pin assignment 의 과정인 것이다. 본 논문에서는 논리회로를 합성하는 expert system의 초보적인 형태를 제안하고 있다.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.9-16
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• 2008

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts two-cube Boolean subexpression pairs from each logic expression. It begins by creating two-cube array, which is extended and compressed with complements of two-cube Boolean subexpressions. Next, the compressed two-cube array is analyzed to extract common subexpressions for several logic expressions. The method is greedy and extracts the best common subexpression. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

• The Journal of Korean Association of Computer Education
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• v.15 no.1
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• pp.65-72
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• 2012

Generally, a logic function has many factored forms. The problem of finding more compact factored form is one of the basic operations in logic synthesis. In this paper, we present a new method for factoring Boolean functions to assist in educational logic designs. Our method for factorization is to implement two-cube Boolean division with supports of an expression. The number of literals in a factored form is a good estimate of the complexity of a logic function. Our empirical evaluation shows the improvements in literal counts over previous other factorization methods.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.20-27
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• 1999

In many synthesis applications, the structure of the synthesized circuit is derived from its BDD functional representation. When synthesizing incompletely specified functions, it is useful to minimize the size of these BDDs using don't cares. In this paper, we present two BDD minimization heuristics that target these synthesis applications. Experimental results show that new techniques yield significantly smaller BDDs compared to existing techniques with manageable run-times.

• The Journal of the Acoustical Society of Korea
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• v.12 no.1
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• pp.27-36
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• 1993

FM방식의 악기음원합성은 해당 악기의 음색과 음정에 맞는 FM의 기본 주파수와 변조 계수를 정하여 신호 파형을 생성하는 것으로, 다른 가, 감산방식 또는 PCM방식 등에 비해 비교적 간단한 구조로 다양한 악기음원합성이 가능하다. 따라서 현재 사용되고 있는 개인용 컴퓨터에 부착되는 사운드합성 카드에는 FM방식 음원합성기술이 적용되고 있다. 본 논문에서는 FM방식 음원합성기술을 이용하여 실시간 악기음원합성이 가능한 논리회로를 설계하는데 관한 연구를 기술한다. 본 연구에서는 소프트웨어 프로그래밍에 의해 FM방식 음원합성기의 구조를 설계하고 주요 블록의 최적 변수 값을 실험하였다. 논리회로 설계 및 회로검증은 향후 주문형반도체(ASIC:Application Specific Integrated Circuit)제작을 위해 기존의 표준셀 라이브러리와 주문형반도체 전용 설계시스템을 사용하였다. 회로검증 결과는 간이 평가보드를 제작하고 PC와 접속시켜 생성된 악기음을 직접듣는 주관적 평가방법으로 최종 확인하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.8
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• pp.361-366
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• 2017

For two given logical expressions and, when expression contains the same part of the logical expression as expression, substituting for that part of expression is called a substituted logic expression. If a substituted relation is established between the logical expressions, there is an advantage in that the number of literals used in the whole logical expression can be greatly reduced. However, if the substituted relation is not established, there is no simplification effect obtained from the substituted expression. Previous methods proposed a way to find substituted relations between logical expressions for the given logical expressions themselves, and to calculate substituted expressions if only substitution is possible. In this paper, a new method for performing substitution with addition and revision of logic terms is proposed in order to perform substitution, even though there is no substituted relation between two logic expressions. The proposed method is efficiently implemented using a matrix that finds terms to be added. Then, by covering the matrix that has added terms, substituted logic expressions are found. Experiment results show that the proposed method for several benchmark circuits can reduce the number of literals, compared to existing synthesis tools.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.1-10
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• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.

• Electronics and Telecommunications Trends
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• v.7 no.3
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• pp.96-107
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• 1992

본 고에서는 디지틀 신호 처리기의 효율적 설계를 위해 필수적으로 요구되는 고수준 논리 합성 문제를 다룬다. Behavioral representation으로부터 structural representation으로의 변환은 복잡도의 문제로 인해 제한적으로 연구되어 온 분야로서 최근 VHDL의 표준화에 따라 많은 연구가 요구되고 있다. 본 고에서는 기존의 제안된 방법을 중심으로 VHDL과의 관계 그리고 앞으로의 전망 등에 대해 논한다.

• The Magazine of the IEIE
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• v.20 no.11
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• pp.85-96
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• 1993