• 제목/요약/키워드: 나노패턴

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Development of simulation method for heating line optimization of E-Mold by using commercial CAE softwares (전산모사 프로그램을 이용한 E-MOLD의 Heating Line 배치의 최적화 설계에 관한 연구)

  • Chung, Jae-Youp;Kim, Dong-Hak
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.9 no.6
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    • pp.1754-1759
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    • 2008
  • To produce plastic parts that have fine pattern through conventional injection molding, a lot of difficulties follow. Therefore, rapid heating and cooling methods are good candidates for manufacturing injection-molded parts with micro/nano patterns. In this study, we adopted the E-Mold patent technology. The mold for E-Mold technology has a separate heated core with micro heaters. It is very important to optimize the lay-out of the heaters in heated core because it influences both control and distribution of mold temperature. We developed a optimization method of heating line lay-out by using commercial softwares and compared the output with the experimental results. We used Pro-Engineer Wildfire 2.0 for the mold design, ICEMCFD for mesh generation, and FLUENT for heat transfer simulation. The simulation results showed the temperature profile from $60^{\circ}C$ to $120^{\circ}C$ or $180^{\circ}C$ during heating and cooling process which were compared with the injection molding experiments. We concluded that the simulation could well explain the experimental results. It was shown that the E-Mold optimization design for heater lay-out could be available through the simulation.

중성빔 식각과 중성빔 원자층 식각기술을 이용한 TiN/HfO2 layer gate stack structure의 저 손상 식각공정 개발

  • Yeon, Je-Gwan;Im, Ung-Seon;Park, Jae-Beom;Kim, Lee-Yeon;Gang, Se-Gu;Yeom, Geun-Yeong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.406-406
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    • 2010
  • 일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.

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Laser Fabrication of Graphene-based Materials and Their Application in Electronic Devices (레이저 유도에 의한 그래핀 합성 및 전기/전자 소자 제조 기술)

  • Jeon, Sangheon;Park, Rowoon;Jeong, Jeonghwa;Hong, Suck Won
    • Journal of the Microelectronics and Packaging Society
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    • v.28 no.1
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    • pp.1-12
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    • 2021
  • Here, we introduce a laser-induced graphene synthesis technology and its applications for the electric/electronic device manufacturing process. Recently, the micro/nanopatterning technique of graphene has received great attention for the utilization of these new graphene structures, which shows progress developments at present with a variety of uses in electronic devices. Some examples of practical applications suggested a great potential for the tunable graphene synthetic manners through the control of the laser set-up, such as a selection of the wavelength, power adjustment, and optical techniques. This emerging technology has expandability to electric/electronic devices combined together with existed micro-packaging technology and can be integrated with the new processing steps to be applied for the operation in the fields of biosensors, supercapacitors, electrochemical sensors, etc. We believe that the laser-induced graphene technology introduced in this paper can be easily applied to portable small electronic devices and wearable electronics in the near future.

An Investigation of the Current Squeezing Effect through Measurement and Calculation of the Approach Curve in Scanning Ion Conductivity Microscopy (Scanning Ion Conductivity Microscopy의 Approach Curve에 대한 측정 및 계산을 통한 Current Squeezing 효과의 고찰)

  • Young-Seo Kim;Young-Jun Cho;Han-Kyun Shin;Hyun Park;Jung Han Kim;Hyo-Jong Lee
    • Journal of the Microelectronics and Packaging Society
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    • v.31 no.2
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    • pp.54-62
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    • 2024
  • SICM (Scanning Ion Conductivity Microscopy) is a technique for measuring surface topography in an environment where electrochemical reactions occur, by detecting changes in ion conductivity as a nanopipette tip approaches the sample. This study includes an investigation of the current response curve, known as the approach curve, according to the distance between the tip and the sample. First, a simulation analysis was conducted on the approach curves. Based on the simulation results, then, several measuring experiments were conducted concurrently to analyze the difference between the simulated and measured approach curves. The simulation analysis confirms that the current squeezing effect occurs as the distance between the tip and the sample approaches half the inner radius of the tip. However, through the calculations, the decrease in current density due to the simple reduction in ion channels was found to be much smaller compared to the current squeezing effect measured through actual experiments. This suggests that ion conductivity in nano-scale narrow channels does not simply follow the Nernst-Einstein relationship based on the diffusion coefficients, but also takes into account the fluidic hydrodynamic resistance at the interface created by the tip and the sample. It is expected that SICM can be combined with SECM (Scanning Electrochemical Microscopy) to overcome the limitations of SECM through consecutive measurement of the two techniques, thereby to strengthen the analysis of electrochemical surface reactivity. This could potentially provide groundbreaking help in understanding the local catalytic reactions in electroless plating and the behaviors of organic additives in electroplating for various kinds of patterns used in semiconductor damascene processes and packaging processes.