• Korean Journal of Optics and Photonics
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• v.10 no.2
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• pp.162-168
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• 1999

A new design of four-pass dye laser amplifier affording a narrow-bandwidth pulsed output is demonstrated to suppress the amplified spontaneous emission(ASE) carried by the amplifier output and reduce the possibility of parasitic oscillation in the amplifier. By the direct pulsed amplification of a cw 100 mW dye laser under a Q-switched doubled Nd:YAG laser pumping with energy of 5.6 mJ/pulse, high-peak-power pulsed output with 1.5-mJ energy in 130-MHz bandwidth is obtained corresponding to a power gain greater than $2{\times}10^6$ and an energy efficiency of 27%. The ASE ratio in the four-pass amplifier output is dramatically reduced by using a diffraction grating in the amplifier. Compared with the results obtained from the normal operation of the amplifier with no frequency-selective device, the ASE ratio is reduced by a factor in excess of 10 to remain under 1.5% of the amplifier output whereas the total output energy is slightly increased by ~4%.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.3
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• pp.228-234
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• 2009

In this paper, we present an analytical method that provides fast and efficient evaluation of the power losses and the conversion efficiency for phase-shift controlled full-bridge converter. In the proposed method, the conduction losses are evaluated by calculating the effective values of the ideal current waveform first and incorporating them into an exact equivalent circuit model of the phase-shift controlled full-bridge converter that includes all the parasitic resistances of the circuit components. While the conduction losses are accurately accounted for the synchronous rectification, the core losses are assumed to be negligible in order to simplify the analysis. The validity and accuracy of the proposed method are verified with experiments on a prototype phase-shift controlled full-bridge converter. An excellent correlation between the experiments and theories are obtained for the input voltages of 400V, output voltage 12V and maximum power 720W.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.213-215
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• 2018

본 논문에서는, 경부하 조건에서 저감된 스위칭 손실과 중부하 이상 조건에서 영전압 스위칭을 통해 높은 효율을 가지는 토템폴 브리지리스 역률보상회로를 제안한다. 토템폴 브리지리스 역률보상회로는 기존 브리지 다이오드를 포함한 역률보상회로의 단점인 도통패스 구간의 비교적 많은 소자 수를 통한 도통손실이 다소 큰 단점을 보완한 회로이다. 하지만, 토템폴 브리지리스 역률보상회로는 여전히 하드 스위칭을 통한 손실과 주 파워링 다이오드의 역회복 손실로 인한 단점을 지니고 있게 되며, 그로 인해 현재로써는 높은 효율과 안정적인 동작을 위해서는 부득이 GaN FET를 적용한 개발이 대부분이다. Full 부하 조건의 전류 용량을 고려하여 높은 전류 정격을 가지는 GaN FET를 주 스위치로 활용할 경우, 전류용량과 비례하여 기생 커패시턴스에 의한 손실이 커지기 때문에 경부하 조건에서 높은 효율을 확보하기가 다소 어렵다. 또한 구조상 물리적으로 여전히 하드 스위칭 동작을 할 수 밖에 없기 때문에 서버용 전원장치에서 요구하는 높은 효율을 달성하는데 한계를 지니며 높은 비용이 요구되는 단점을 지니게 된다. 이를 해결하기 위해, 제안하는 회로는 간단한 회로를 통해 경부하 조건에서 저감된 스위칭 손실과 중부하 이상 조건에서 소프트 스위칭을 만족하여 전체 부하 조건에서 기존의 GaN FET을 활용한 토템폴 구조 대비 높은 효율을 가지게 된다. 또한, 토템폴 구조임에도 불구하고 중부하 이상 영역에서 소프트 스위칭 동작을 통해 주 스위치를 비교적 저렴하고 신뢰성이 검증된 Si-MOSFET을 적용할 수 있다는 장점을 지닌다. 제안하는 회로의 효용성을 증명하기 위해, 하이라인 입력 전압과 750W 출력 조건에서 실험을 진행하였다.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.9
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• pp.805-811
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• 2016

This paper proposes an estimation algorithm of phase currents of inverter systems with the planar bus bars for brush-less DC (BLDC) motors. The planar bus bar can improve the characteristic of the EMC(Electro-Magnetic Compatibility). In these inverters, a single current sensor of the dc-link measures the sum of a smooth capacitor current and phase currents of brush-less DC motor. Thus, it is essential to extract phase currents from the measured single current to control BLDC motor. Therefore, in this paper, the phase current is estimated by analyzing equivalent circuits of the BLDCM in ON and OFF periods of switching elements. The usefulness of the proposed algorithm is verified through experimental results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.139-145
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• 2008

In this paper, a microstrip surface wave antenna(SWA) with a frequency selective surface structure(FSS) is designed and measured. A microstrip SWA has many advantages such as low profile, low weight, easy fabrication, and compatibility with monolithic microwave integrated circuits(MMIC). In addition, it has demonstrated monopole like beam patterns. The microstrip SWA consists of two parts : a center-fed modified microstrip patch to excite surface wave, and a periodic patches to support the propagation of the surface waves. To obtain wide bandwidth, the ring type parasitic element is inserted and the circular patch is selected for the unit element in FSS structure. Experimental results show that the microstrip SWA has monopole like beam patterns at 5.9GHz. Impedance bandwidth and gain is 12% and 5.6dBi.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.5
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• pp.423-431
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• 2001

This paper proposes a new active common-mode voltage damper circuit that is capable of suppressing a common-mode voltage produced in the PWM VSI-fed induction motor drives. The new active common mode voltage damper is consists of a four-level half-bridge Inverter and a common mode transformer with a blocking capacitor. In order to reduce the common mode voltage and high frequency leakage current the active common mode damper applies to the PWM inverter system the compensated voltage of which the amplitude is the same as the common mode voltage and of which the polarity is opposite to the common mode voltage. Simulated using P-SPICE and experimental results show that common-mode voltage damper makes contributions to reducing a high frequency leakage current and common-mode voltage.

• Journal of IKEEE
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• v.27 no.4
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• pp.450-455
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• 2023

Among single-phase photovoltaic inverters that can avoid excessive leakage current caused by the large parasitic capacitance of photovoltaic panels, a boost converter followed by a half-bridge inverter is the simplest and has the smallest leakage current. However, due to the high DC-link voltage, the rated voltage of the switching devices is high and the switching loss is large. This paper proposes a new circuit topology which can operate as a buck-boost inverter by adding two bidirectional switches to the output side of the half-bridge inverter instead of removing the boost converter. By reducing two stages of power conversion through the high-voltage DC-link to one stage, power loss can be reduced without increasing costs and leakage current. The feasibility of the proposed circuit topology is verified by computer simulation and power loss calculation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1104-1112
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• 2013

This paper presents a wideband Colpitts voltage controlled oscillator(VCO) with nanosecond startup time and a center frequency of 8.35 GHz for a new bubble-type motion detector that has a bubble-layer detection zone at the specific distance from itself. The VCO circuit consists of two parts; one is a negative resistance part with a HEMT device and Colpitts feedback structure and the other is a resonator part with a varactor diode and shorted shunt microstrip line. The shorted shunt microstrip line and series capacitor are utilized to compensate for the input reactance of the packaged HEMT that changes from capacitive values to inductive values at 8.1 GHz due to parasitic package inductance. By tuning the feedback capacitors which determine negative resistance values, this paper also investigates startup time improvement with the negative resistance variation and tuning bandwidth improvement with the reactance slope variation of the negative resistance part. The VCO measurement shows the tuning bandwidth of 2.3 GHz(28 %), the output power of 4.1~7.5 dBm and the startup time of less than 2 nsec.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.12
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• pp.7287-7291
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• 2014

A CDTA (current differencing transconductance amplifier) is an active building block for current mode analog signal processing with the advantages of high linearity and a wide frequency bandwidth. In addition, it can generate a stable voltage because all the differencing input current flows to the grounded devices. In this paper, a new small signal equivalent circuit is proposed to analyze a CDTA. The proposed small signal equivalent circuit provides greater precision in analyzing the magnitude and frequency response than its previous counterparts because it considers the parasitic components of the input, internal and output terminal. In addition, observations of the changes made in various devices, such as the resistor (Rz) confirmed that those devices heavily influence the characteristics of CDTA. The designed parameters of the proposed small signal equivalent circuit of the CDTA provides convenience and accuracy in the further design of analog integrated circuits. For verification purposes, a 2.5 MHz low pass filter was designed on the HSPICE simulation program using the proposed small signal equivalent circuit of CDTA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.105-112
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• 2009

In this paper, we investigated abnormal ESD failure on guard-rings in the smart power IC fabricated with $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology. Initially, ESD failure occurred below 200 V in the Machine Model (MM) test due to current crowding in the parasitic diode associated with the guard-rings which are generally adopted to prevent latch-up in high voltage devices. Optical Beam Induced Resistance Charge (OBIRCH) and Scanning Electronic Microscope (SEM) were used to find the failure spot and 3-D TCAD was used to verify cause of failure. According to the simulation results, excessive current flows at the comer of the guard-ring isolated by Local Oxidation of Silicon (LOCOS) in the ESD event. Eventually, the ESD failure occurs at that comer of the guard-ring. The modified comer design of the guard-ring is proposed to resolve such ESD failure. The test chips designed by the proposed modification passed MM test over 200 V. Analyzing the test chips statistically, ESD immunity was increased over 20 % in MM mode test. In order to avoid such ESD failure, the automatic method to check the weak point in the guard-ring is also proposed by modifying the Design Rule Check (DRC) used in BCD technology. This DRC was used to check other similar products and 24 errors were found. After correcting the errors, the measured ESD level fulfilled the general industry specification such as HBM 2000 V and MM 200V.