• Journal of Broadcast Engineering
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• v.27 no.1
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• pp.31-43
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• 2022

Traditional video compression has developed so far based on hybrid compression methods through motion prediction, residual coding, and quantization. With the rapid development of technology through artificial neural networks in recent years, research on image compression and video compression based on artificial neural networks is also progressing rapidly, showing competitiveness compared to the performance of traditional video compression codecs. In this paper, a new method capable of improving the performance of such an artificial neural network-based video compression model is presented. Basically, we take the rate-distortion optimization method using the auto-encoder and entropy model adopted by the existing learned video compression model and shifts some components of the latent information that are difficult for entropy model to estimate when transmitting compressed latent representation to the decoder side from the encoder side, and finally compensates the distortion of lost information. In this way, the existing neural network based video compression framework, MFVC (Motion Free Video Compression) is improved and the BDBR (Bjøntegaard Delta-Rate) calculated based on H.264 is nearly twice the amount of bits (-27%) of MFVC (-14%). The proposed method has the advantage of being widely applicable to neural network based image or video compression technologies, not only to MFVC, but also to models using latent information and entropy model.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.327-336
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• 2007

Lots of effort toward design optimizations have been paid for a cost-effective system design in various ways from a transistor level to RTL designs. In this paper, we propose a bit level optimization of an adder design for expanding its design space. For the bit-level optimization, a heterogeneous adder organization utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Then, we develop an optimization method based on Integer Linear Programming to search the expanded design space of the heterogeneous adder. The novelty of the Proposed architecture and optimization method is introducing a bit level reconstruction/recombination of IPs which have same functionality but different speed and area characteristics for producing more find-grained delay-area optimization.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4780-4785
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• 2012

As many mobile devices such as smart phones and tablets are widely spread, optimized mobile video encoder used during video recording application is needed. In this paper, we implemented H.264/AVC base profile video encoder on a mobile device and empirically optimized control parameters of the encoder. As the experiment, we more than 100 test cases were designed with varying Lagrangian optimization, Hadamard Transform, search range, I-frame period, and reference frames. During the experiment, we measured picture quality, bit-rate, encoding time, motion estimation time, and power consumption. From the result, we can determine optimal values for the H.264 control parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.6
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• pp.86-93
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• 2009

We investigate lattice-reduction-aided precoding techniques for multi-user multiple-input multiple-output (MIMO) channels. When assuming full knowledge of the channel state information only at the transmitter, a vector perturbation (VP) is a promising precoding scheme that approaches sum capacity and has simple receiver. However, its encoding is nondeterministic polynomial time (NP)-hard problem. Vector perturbation using lattice reduction algorithms can remarkably reduce its encoding complexity. In this paper, we propose a vector perturbation scheme using Seysen's lattice reduction (VP-SLR) with simultaneously reducing primal basis and dual one. Simulation results show that the proposed VP-SLR has better bit error rate (BER) and larger capacity than vector perturbation with Lenstra-Lenstra-Lovasz lattice reduction (VP-LLL) in addition to less encoding complexity.

• The Journal of the Acoustical Society of Korea
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• v.24 no.7
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• pp.402-409
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• 2005

In this paper. we propose a coding method using a matching pursuit algorithm in a strongly periodic highband signal. Also. we propose an efficient quantizer for the estimated parameters : spectral magnitude and phase. Based on the error concealment principle and sinusoidal model. the MP algorithm requires the high-precision pitch period estimation. To estimate more accurate pitch period. the refined pitch obtained from lowband speech is used. which increases the efficiency of bit allocation. The spectral magnitude parameters are quantized by the method which is combined with MDCT (Modified Discrete Cosine Transform) and multi-stage structure. The spectral phase quantizer uses the $2{\pi}$ modular characteristic of phases and the weighted function by spectral magnitudes. To evaluate the efficiency of the proposed method. we applied it to analysis-by-synthesis system. Furthermore we suggest the possibillity of scalable wideband speech codecs based on band-split structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.72-81
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• 2002

A new high-performance DSP architecture is proposed, which behaves as a coprocessor of a 32bit microcontroller. Because the proposed DSP architecture is a dual MAC(Multiply and Accumulate) DSP architecture, it can process efficiently a number of SOP(sum of product) operations used in many DSP applications. In order to efficiently perform other operations such as pure additions without any restriction, a MAC is composed of a multiplier and a ALU placed in parallel. In addition, it is a 3-way superscalar architecture, which can issue 3 instructions at a time. The benchmark results with 3 thor dual MAC DSPs show that the proposed DSP has the best performance. Futhermore, it is proven that the proposed DSP is more efficient in memory usage, although the performance is comparable in some algorithms such as Viterbi decoding and FFT butterfly.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1183-1188
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• 2015

The FM-QCSK(: Frequency Modulated Quadrature Chaos Shift Keying) system is one of the most efficient systems in chaotic literature. One of the problems in this system is that half the bit duration is used for sending a chaotic reference signal which leads to increase the energy losses and reduces the data rate. In this paper, a novel scheme to enhance the performance of FM-QCSK system has been proposed. With the proposed scheme, FM-QCSK would be able to operate at higher data rates with reduced BER(: Bit Error Rate) and energy consumption. The basic modification introduced by the proposed scheme is the use one reference chaotic signal to transmit multi information signals in both in-phase and quadrature-phase channels. The results showed that the proposed scheme have achieved more than 3 dB gains in SNR for AWGN channels respectively at $BER=10^{-3}$ over the conventional one. The results also showed that the optimum number information signals can be send per reference signal is 8.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.141-150
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• 2007

This paper proposes new Steganographic model for VoIP that has very effective method using low bit encoding. Most of Steganographic models using Low bit Encoding have two disadvantages; one is that the existence of hidden secret message can be easily detected by auditory, the other is that the capacity of stego data is low. To solve these problems, this method embed more than one bit in inaudible range, so this method can improve the capacity of the hidden message in cover data. The embedding bit position is determined by using a pseudo random number generator which has seed with remaining message length, so it is hard to detect the stego data produced by the proposed method. This proposed model is able to use not only to communicate wave file with hidden message in VoIP environment but also to hide vary information which is user basic information, authentication system, etc.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.32-40
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• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.