• Review of KIISC
• /
• v.33 no.1
• /
• pp.31-39
• /
• 2023

1994년 피터 쇼어에 의해, 대규모 큐비트 연산이 가능한 양자 컴퓨터가 개발된다면 RSA와 같은 현재 공개키 암호 알고리즘이 공격을 당할 수 있음을 이론적으로 가능하게 해주는 쇼어 알고리즘이 소개된 이후, 공개키암호시스템의 붕괴에 대한 가능성은 점점 현실로 다가오고 있다. 물론, 공개키암호시스템은 향후 10~20년은 여전히 안전할 가능성이 높지만, NIST는 최악의 상황에 대비하여 2017년부터 양자내성암호(Post-Quantum Cryptography)에 대한 표준화 작업을 수행하고 있으며, 2022년 4종의 표준화 대상 알고리즘을 선정한 바 있다. 이 중에서도 NIST는 Crystals-Kyber(PKE/KEM)와 Crystals-Dilithium(DSA)를 기본 알고리즘으로 언급하며 우수한 성능과 강한 보안성으로 대부분의 응용에서 잘 동작할 것이라고 예측한 바 있다. 이들 알고리즘은 3라운드의 경쟁 알고리즘 대비 보안 강도가 다소 약한 측면에 있었음에도 우수한 성능, 다양한 환경에서의 적용 가능성 등에 따라 선정된 것으로 보인다. 그럼에도 최근 일부 연구에서는 하이브리드 Dual 공격을 제안함으로써 최초 주장하는 보안 강도와 비교하여 안전성이 더 약화될 가능성이 제기된 바 있다. 본 논문에서는 이들 알고리즘에 대한 안전성 분석 방법을 살펴보고, 최근 논문에서 제기된 새로운 안전성 분석 방법과 그에 따르는 보안 강도를 분석한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2022.06a
• /
• pp.1245-1248
• /
• 2022

본 논문에서는 사용자가 보다 간편하게 볼류메트릭 비디오를 소비할 수 있도록 볼류메트릭 비디오 기본 플레이어를 구현하고, 구현한 플레이어에 대하여 성능평가를 진행한다. 본 논문에서 구현한 볼류메트릭 비디오 플레이어는 Draco 와 V-PCC 를 복호화기로 지원하며, 압축 전의 포인트 클라우드 데이터와 Draco 와 V-PCC 로 압축한 비트스트림에 대하여 성능 평가를 진행하였다. 플레이어의 성능을 평가한 결과를 통해 초기 충분한 량의 프레임을 버퍼에 확보할 만큼의 초기 지연시간을 설정하지 않는 이상, 볼류메트릭 비디오를 30fps 이상으로 소비하기에는 어려움이 있음을 확인하였다. 이를 토대로 현재 볼류메트릭 비디오 재생을 위한 기술적 한계를 살펴보고, 볼류메트릭 비디오 플레이어의 성능 향상을 위한 향후 연구개발 방향에 대하여 논의한다.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.3
• /
• pp.152-162
• /
• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.2 s.344
• /
• pp.51-59
• /
• 2006

Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.9
• /
• pp.907-915
• /
• 2002

In this paper, a compact digital phase shifter to be used an active phased array antenna system for satellite communications was proposed. The even and odd mode analysis for a given reflection-type phase shifter, which uses a folded hybrid coupler as a base element, was performed and the design parameters were derived. Also, to verify experimentally the electrical performances of the proposed structure, X-band 4-bit digital phase shifter was designed and fabricated using Teflon soft substrate $({\varepsilon}_r; =\;2.17)$. Its circuit size was less than 3.5 cm $\times$ 3.0 cm, and it exhibited at least 50 % size reduction as compared with the conventional unfolded configuration. The experimental results of the fabricated phase shifter showed that the average insertion loss and insertion loss variation were less than 3.5 dB, $\pm$ 0.6 dB within the operating band, 7.9 ~ 8.4 GHz, respectively. And, input and output return loss were more than 10 dB, respectively. Also, the phase response of the phase shifter showed 4-bit operation with $\pm$3$^{\circ}$ rms phase error.

• Journal of Korea Multimedia Society
• /
• v.15 no.4
• /
• pp.492-500
• /
• 2012

In this paper, improved contour region coding method is proposed to accomplish better depth map coding performance. First of all, in order to use correlation between color video and depth map, a structure in SVC is applied to 3DVC. This can reduce bit-rate of the depth map while supporting the video to be transferred via various collection of network. As the depth map is mainly used to synthesize videos from different views, corrupted contour region can damage the overall quality of video. We hereby adapt a new differential quantization method when separating the contour region. The experimental results show that the proposed method can improve video quality by 0.06~0.5dB which translate the bit rate saving by 0.1~1.15%, when compared to the reference software.

• The Journal of the Acoustical Society of Korea
• /
• v.19 no.7
• /
• pp.42-47
• /
• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• The KIPS Transactions:PartD
• /
• v.19D no.2
• /
• pp.151-160
• /
• 2012

Most of the distributed high-dimensional indexing structures provide a reasonable search performance especially when the dataset is uniformly distributed. However, in case when the dataset is clustered or skewed, the search performances gradually degrade as compared with the uniformly distributed dataset. We propose a method of improving the k-nearest neighbor search performance for the distributed vector approximation-tree based on the strongly clustered or skewed dataset. The basic idea is to compute volumes of the leaf nodes on the top-tree of a distributed vector approximation-tree and to assign different number of bits to them in order to assure an identification performance of vector approximation. In other words, it can be done by assigning more bits to the high-density clusters. We conducted experiments to compare the search performance with the distributed hybrid spill-tree and distributed vector approximation-tree by using the synthetic and real data sets. The experimental results show that our proposed scheme provides consistent results with significant performance improvements of the distributed vector approximation-tree for strongly clustered or skewed datasets.

• Journal of Sensor Science and Technology
• /
• v.6 no.2
• /
• pp.137-144
• /
• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.724-727
• /
• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.