• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.163-166
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• 2004

본 논문은 3차원 형상 인식시스템으로부터 스캔 한 3차일 영상 데이터의 깊이정보에 3차원 에지를 추출하여 워터마크를 삽입하는 알고리즘을 제안한다. 제안한 알고리즘에서는 3차원 수직 평형 형상 인식기로 object scanning을 한 데이터 값들을 추출한다. 이 추출된 값들의 특성은 2차원 영상 즉 x, y축에 각각의 픽셀에 깊이정보를 가지는 3차원영상으로서 기존의 3차원영상과는 다른 차이를 가지며 영상의 품질이 우수하며 많은vertex 정보와 메쉬 정보를 가지고 있다. 따라서 획득된 데이터에서 x좌표와 y좌표는 영상에 있어서 위치를 나타내는 정보이고, T좌표는 3차원영상을 형성하는 깊이 정보들이다. 3차원 형상 인식시스템에서 스캔 한 3차원 얼굴영상으로부터 에지를 검출하여 에지가 존재하는 위치에 워터마크를 삽입하는 알고리즘을 제안하였다. 본 논문에서 제안한 워터마킹 알고리즘의 성능 평가를 위한 모의실험 한 결과 워터마크가 삽입된 모텔의 절단(cropping), 리메쉬(remesh) 및 메쉬간소화(mesh simplification) 공격에 대한 견고성이 우수함을 확인함으로써 3차원형상 인식 시스템에 직접적인 워터마크 삽입이 가능함을 증명하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.596-598
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• 2010

본 논문에서는 의료영상 중 X-ray 영상을 대상으로 영상을 분류하고 분류 결과에 따라 다중 키워드를 생성하는 방법을 제시한다. X-ray영상은 대부분 그레이 영상임으로 Local Binary Patterns (LBP)을 이용하여 픽셀간의 연관성을 특징으로 추출하고, 실시간 학습 및 분류가 가능한 Random Forests 분류기로 영상들을 30개의 클래스로 분류한다. 또한, 미리 정의된 신체 부위간의 관계 가중치를 분류 스코어에 결합하여 신뢰값을 생성하고 이를 기반으로 영상에 대해 다중 주석을 부여하게 된다. 이렇게 부여된 다중 주석은 키워드 기반의 의료영상을 가능케 함으로 보다 쉽고 효율적인 검색 환경을 제공할 수 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.966-968
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• 2021

본 논문에서는 효과적인 고해상도 비디오 데이터의 처리를 위하여 부호화기 내에서 참조 영상을 저장하는 프레임 메모리를 압축하는 방법을 제안한다. 프레임 메모리는 응용분야의 특성상 무손실 압축 및 저 복잡도를 갖는 방법이 요구되는데, 블록 단위의 PCT 를 이용하여 픽셀 사이의 상관도를 제거하고, 적응적 GR 부호기를 이용하여 최종 비트열을 구성하여 압축하는 방법을 제안한다. 다양한 테스트 영상을 대상으로 실험한 결과 제안하는 방법이 기존의 압축 방법에 비해 압축 성능이 우수하면서 실행 시간으로 측정한 복잡도 측면에서 유사한 성능을 나타냄을 확인하였다. 압축 성능과 복잡도의 두가지 측면을 종합적으로 판단한 결과 제안하는 방법이 기존의 방법에 비해 충분히 경쟁력이 있음을 알 수 있다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.663-674
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• 2003

Bump mapping is a technique that represents the detailed parts of the object surface, such as a perturberance of the skin of a peanut, using the geometry mapping without complex modeling. However, the hardware implementation for bump mapping is considerable, because a large amount of per pixel computation, including the normal vector shading, is required. In this paper, we propose a new bump mapping algorithm using the polar coordinate system and its hardware architecture. Compared with other existing architectures, our approach performs bump mapping effectively by using a new vector rotation method for transformation into the reference space and minimizing illumination calculation. Consequently, our proposed architecture reduces a large amount of computation and hardware requirements.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.11-15
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• 2015

In this paper, we introduce three modulation codes of the code rate 1/2 with different minimum distances, respectively, and investigate the performance of the codes according to the minimum distance. We simulate the codes in accordance with blur and misalignment. As the minimum distance increases, the complexity of encoder and decoder also grows. However, it can improve the error correcting capability and shows good performance with blur and misalignment.

• Journal of Korea Multimedia Society
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• v.6 no.5
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• pp.778-787
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• 2003

Intrusion detection systems based on rules are not efficient for mutated attacks, because they need additional rules for the variations. In this paper, we propose an intrusion detection system using the time delay neural network. Packets on the network can be considered as gray images of which pixels represent bytes of them. Using this continuous packet images, we construct a neural network classifier that discriminates between normal and abnormal packet flows. The system deals well with various mutated attacks, as well as well known attacks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.145-148
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• 2016

In this paper, we propose a design of Intra Prediction angular mode decision for high-performance HEVC encoder. Intra Prediction works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original image pixel, using an algorithm that determines Angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9k and operating speed is 2GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1681-1688
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• 2017

In this paper, we implemented a high-speed signal processing hardware system for Color Line Scan Camera using FPGA and Nor-Flash. The existing hardware system mainly processed by high-speed DSP based on software and it was a method of detecting defects mainly by RGB individual logic, however we suggested defect detection hardware using RGB-HSL hardware converter, FIFO, HSL Full-Color Defect Decoder and Image Frame Buffer. The defect detection hardware is composed of hardware look-up table in converting RGB to HSL and 4K HSL Full-Color Defect Decoder with high resolution. In addition, we included an image frame for comprehensive image processing based on two dimensional image by line data accumulation instead of local image processing based on line data. As a result, we can apply the implemented system to the grain sorting machine for the sorting of peanuts effectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.

• Journal of the Korean Society of Radiology
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• v.9 no.6
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• pp.403-408
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• 2015

Hard X-ray has been widely used in medical and industrial fields because it can be applied to observe the inside of a sample. Computed tomography provides sectional images of the sample through the reconstruction of the projection images. The quality of sectional images strongly depends on that of projection images. Ring artifact appeared on the seconal image can be made by the abnormal pixels of the detector used. In this study, we examine the ring artifact ratio in the circle phantom as a function of detection error of the detector used in computed tomography. The ring artifact increased with the increment of detection error under parallel and fan beam geometries and strongly increased near the center of rotation. The corrections, dead pixel and flat field corrections, for the images taken with the detector are required before the image reconstruction process to reduce the ring artifact in the computed tomography.