• Journal of Korea Game Society
• /
• v.20 no.3
• /
• pp.35-44
• /
• 2020

In this study, we propose a reliable command placement recognition algorithm using tangible commands blocks developed for our coding puzzle platform, and present its performance measurement results on an Augmented Reality testbed environment. As a result, it can recognize up to 30 tangible blocks simultaneously and their placements within 5 seconds reliably. It is successfully ported to an existing coding puzzle mobile app and can operate an IoT attached robot via bluetooth connected mobile app.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1738-1739
• /
• 2007

초음파 모터는 고정자와 회전자를 가압마찰하기 위해서 내부에 원형 판 스프링을 이용하고 있다. 출력 토크를 높이기 위해서 이러한 내부 스프링의 강도를 크게 하면 홀딩 토크 역시 커지게 된다. 이로 인하여 기동 시 많은 전류가 소모되며 일반적인 구동 파라미터에 따른 속도 특성 등 기존의 스프링 강도를 지닌 초음파모터(모델명 : 신생공업사(일) USR60-s1)의 특성과는 전혀 다른 특성을 보인다. 본 논문에서는 스프링이 강화된 새로운 타입의 초음파모터(모델명 : 신생공업사(일) USR60-s3)를 가지고 무부하 시의 속도 특성을 실험하였다. 이를 위해 FPGA를 이용해서 디지털 다중 초음파 모터 제어기를 설계하였고, 2상입력 전원의 주파수, 위상차, 주파수-위상차 다중 파라미터 등을 조절하면서 무부하 속도 특성을 측정하였다. 그 결과 홀딩토크가 강화된 초음파 모터의 경우 일반적인 기존 초음파 모터와 비교했을 때 전혀 다른 특성을 보이고, 위상차-주파수 다중 파라미터 조절방식이 조절방식임을 보인다.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.6
• /
• pp.2747-2753
• /
• 2011

In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.34 no.10
• /
• pp.1385-1391
• /
• 2010

In this study, we present small-size, low-power, and high-speed electromagnetic flapping shutters for phone cameras. These shutters are composed of trapezoidal twin blades suspended by H-type torsional springs. The existing electrostatic rolling and flapping shutters need high input voltage, while the existing electromagnetic rotating shutters are too big to be used for phone cameras. To achieve low-power and high-speed angle motion for small-size electromagnetic flapping shutters for camera phones, low-inertia trapezoidal twin blades, each suspended by the low-stiffness H-type torsional springs, are employed. The electromagnetic flapping shutters used in this experimental study have steady-state rotational angles of $48.8{\pm}1.4^{\circ}$ and $64.4{\pm}1.0^{\circ}$ in the magentic fields of 0.15 T and 0.30 T, respectively, for an input current of 60 mA; the maximum overshoot angles are $80.2{\pm}3.5^{\circ}$ and $90.0{\pm}1.0^{\circ}$ in the magentic fields of 0.15 T and 0.30 T, respectively. The rising/settling times of the shutter while opening are 1.0 ms/20.0 ms, while those while closing are 1.7 ms/10.3 ms. Thus, we experimentally demonstrated that the smallsize (${\sim}8{\times}8{\times}2\;mm^3$), low-power (${\leq}60\;mA$), and high-speed (~1/370 s) electromagnetic flapping shutters are suitable for phone cameras.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3235-3245
• /
• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.13-20
• /
• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.5
• /
• pp.1193-1200
• /
• 2008

This paper describes a developed 5Watt power amplifier module fer mobile communication system using Gallium Nitride (GaN) devices. Three amplification stages such as pre-amplifier, driver amplifier, and power amplifier have been fabricated and measured separately in advance for incorporating the total power amplifier module and estimating the performances. In addition, a defected ground structure is combined with the output stage of the power amplifier module for improving harmonic rejection and adjacent channel power (ACP) characteristics. The measured performances of the GaN power amplifier module include 58dB,min of gain, 37dBm,min of output power, 50dBc,min of harmonic rejection, 35dBc,min of IMD3 for 2-tone input, and 35dBc,min of ACP at 2.1GHz frequency band.

• Journal of Advanced Navigation Technology
• /
• v.21 no.6
• /
• pp.626-632
• /
• 2017

This paper describes a high power amplifier combining eight low power amplifiers using a radial power combiner with low insertion loss. The radial power combiner is a non-resonant type combiner with 8 input ports and is implemented by microstrip transmission line. The combiner characteristics designed at operating frequency of 1.045 GHz have an insertion loss of 0.7 dB and a return loss of more than 12 dB. Also, the low power amplifier used was designed with AFT27S010NT1 transistor and designed to satisfy the same gain, phase and constant output characteristic at operating frequency. The high power amplifier, which combiners the radial power combiner and the drive amplifier of 8 W output by driving low power amplifiers obtained the output characteristic of 33 W at operating frequency of 1.045 GHz. Also, the change of the output characteristic of the amplifier using the radial combiner was graceful degradation when the low power amplifier failed one by one.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.10
• /
• pp.91-97
• /
• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.63-70
• /
• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.