• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.16-23
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• 2007

For a fully depleted SOI type symmetric double gate MOSFET, a simple expression for the threshold voltage has been derived in a closed-form To solve analytically the 2D Poisson's equation in a silicon body, the two-dimensional potential distribution is assumed approximately as a polynomial of fourth-order of x, vertical coordinate perpendicular to the silicon channel. From the derived expression for the surface potential, the threshold voltage can be obtained as a simple closed-form. Simulation result shows that the threshold voltage is exponentially dependent on channel length for the range of channel length up to $0.01\;[{\mu}m]$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.17-24
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• 2004

Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.110-111
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• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.405-405
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• 2012

에너지 갭의 크기가 큰 ZnO는 큰 여기자 결합과 높은 화학적 안정도를 가지고 있기 때문에 전자소자 및 광소자로 많이 응용되고 있다. ZnO는 광학적 및 전기적 성질의 여러 가지 장점 때문에 메모리, 나노발전기, 트랜지스터, 태양전지, 광탐지기 및 레이저와 같은 여러 분야에 많이 사용되고 있다. Zn와 쉘 구조가 비슷한 Cu 불순물은 우수한 luminescence activator이고 다양한 불순물 레벨을 만들기 때문에 전기적 및 광학적 특성을 변화하는데 좋은 도핑 물질이다. Cu가 도핑된 ZnO 나노구조를 전기화학적 증착법을 이용하여 형성하고, 형성시간의 변화에 따른 구조적 및 광학적 성질에 대한 관찰하였다. ITO 코팅된 유리 기판에 전기화학증착법을 이용하여 Cu 도핑된 ZnO를 성장하였다. Sputtering, pulsed laser vapor deposition, 화학기상증착, atomic layer epitaxy, 전자빔증발법 등으로 Cu 도핑된 ZnO 나노구조를 형성하지만 본 연구에서는 낮은 온도와 간단한 공정으로, 속도가 빠르고 가격이 낮아 경제적인 면에서 효율적인 전기 화학증착법으로 성장하였다. 반복실험을 통하여 Cu의 도핑 농도는 Zn과 Cu의 비율이 97:3이 되도록, ITO 양극과 Pt 음극의 전위차가 -0.75V로 실험조건을 고정하였고, 성장시간을 각각 5분, 10분, 20분으로 변화하였다. 주사전자현미경 사진에서 Cu 도핑된 ZnO는 성장 시간이 증가함에 따라 나노세선 형태에서 나노로드 형태로 변하였다. X-선 회절 측정결과에서 성장시간이 변화함에 따라 피크 위치의 변화를 관찰하였다. 광루미네센스 측정 결과는 Oxygen 공핍의 증가로 보이는 500~600 nm 대의 파장에서 나타난 피크의 위치가 에너지가 큰 쪽으로 증가하였다. 위 결과로부터 성장 시간에 따른 Cu 도핑된 ZnO의 구조적 및 광학적 특성변화를 관찰하였고, 이 연구 결과는 Cu 도핑된 ZnO 나노구조 기반 전자소자 및 광소자에 응용 가능성을 보여주고 있다.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.53.1-53.1
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• 2010

결정질 실리콘 태양전지의 효율을 향상시키기 위하여 수광면에 서로 다른 도핑농도를 가지는 고농도 도핑영역과 저농도 도핑영역으로 이루어진 emitter를 형성하는 것이 요구되며 이를 selective emitter라 칭한다. Selective emitter를 형성하면 고농도 도핑영역에서 금속전극과 저항 접촉이 잘 형성되기 때문에 직렬 저항이 최소화되고 저농도 도핑영역에서는 전하 재결합의 감소로 인하여 태양전지의 변환효율이 상승하는 이점이 있다. Selective emitter의 형성방법은 이미 다양한 방법이 제안되고 있으나, 본 연구에서는 기존에 제시된 방법과는 다르게 열산화 시 dopant redistribution에 의한 Boron depletion 현상을 이용하여 selective emitter를 형성하는 방법을 제안하였고, 이를 Simulation을 통하여 검증하였다. 초기 emitter 확산 후 junction depth는 0.478um, 면저항은 $104.2{\Omega}/sq.$ 이었으며, nitride masking layer 두께는 0.3um로 설정하였다. $1100^{\circ}C$에서 30분간 습식산화 공정을 거친 후 nitride mask가 있는 부분의 junction depth는 1.48um, 면저항은 $89.1{\Omega}/sq$의 값을 보였고, 산화막이 형성된 부분의 junction depth는 1.16um, 면저항은 $261.8{\Omega}/sq$의 값을 보였다. 위 조건의 구조를 가진 태양전지의 변환 효율은 19.28%의 값을 나타내었고 Voc, Jsc 및 fill factor는 각각 645.08mV, $36.26mA/cm^2$, 82.42%의 값을 보였다. 한편 일반적인 구조로 설정한 태양전지의 변환 효율, Voc, Isc 및 fill factor는 각각 18.73%, 644.86mV, $36.26mA/cm^2$, 80.09%의 값을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.25-32
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• 2005

In this paper, it is attempted to provide a unified explanation for typical short channel GaAs MESFET’s and SOI-structured Si JFET's behaviors such as: i) drain voltage-induced threshold voltage roll-off, ii) finite output ac resistance beyond the saturation, and iii) weak dependence of the drain saturation current on the channel length. Replacing the conventional GCA with a new assumption that is suggested in order to include the longitudinal field variation, and taking into account the channel current continuity and the field-dependent mobility, we can derive the two-dimensional potential in both depletion region and undepleted conducting channel. Obtained expressions for the threshold voltage and the drain current will be considerably accurate over the entire operating region. Moreover, in comparison with the conventional channel length shortening models, our model seems to be more reasonable in explaining the Early effect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.21-28
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• 2008

In this paper, we suggest an analytical model that can derive the I-V characteristics in the saturation region of a short channel GaAs MESFET. Instead of the pinch-off concept that has been used in the conventional models we can derive the two-dimensional potential in the depletion region in order that the velocity saturation region cannot be pinched-off and the current continuity condition can be satisfied. Obtained expression for the velocity saturation length is expressed in terms of the total channel length, channel doping density, gate voltage, and drain voltage. Compared with the conventional channel length shortening models, the present model seems to be considerably accurate and more reasonable in explaining the Early effect.

• Journal of the Korean Vacuum Society
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• v.22 no.6
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• pp.335-340
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• 2013

This paper is for the simulation design to enhance the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess and channel structures has been simulated and analyzed for the breakdown of the MHEMT devices. The fully removed recess structure at the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to almost 4 V as the saturation current at gate voltage of 0 V is reduced from 90 mA to 60 mA at drain voltage of 2 V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier and the $Si_3N_4$ passivation layers deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer and thus the impact ionization in the channel become smaller. In addition, the replaced InGaAs/InP composite channel with the same thickness in the same asymmetrically recessed structure increases the breakdown voltage to 5 V due to the smaller impact ionization and mobility of the InP layer at high drain voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1349-1354
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• 2011

In this work, we fabricated the CdZnS/CdTe heterojunction and investigated the C-V characteristics to determine the depletion width and the charge density distribution. A parallel experiment on CdS/CdTe heterojunction was also carried out for comparison. The depletion region width, for CdZnS/CdTe heterojunction, was nearly constant, regardless of bias voltage. However, the depletion region was wider than that of CdS/CdTe heterojunction due to high resistivity of CdZnS film. The interface charge density of CdZnS/CdTe heterojunction was increased linearly with the bias voltage and showed lower values than those for CdS/CdTe junction. The open circuit voltage of CdZnS/CdTe heterojunction solar cells increased with zinc mole ratio due to reducing of the electron affinity difference between CdZnS and CdTe films. However, the increase of series resistance due to the high resistivity of Cd1-xZnxS films results in reducing conversion efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1647-1652
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• 2010

A CdS film has been used as a window layer in CdTe and Cu(In,Ga)$Se_2$ thin films solar cell. Partial substitution of Zn for Cd increases the photocurrent and the open-circuit voltage by providing a match in the electron affinities of the two materials and the higher band gap. In this paper, CdZnS/CdTe and CdS/CdTe heterojunctions were fabricated and the electrical characteristics were investigated. Current-voltage-temperature measurements showed that the current transport for CdS/CdTe heterojunction was controlled by both tunneling and interface recombination. However, CdZnS/CdTe heterojunction displayed different current transport mechanism with the operating temperature. For above room temperature, the current transport of device was generation/recombination in the depletion region and was the leakage current and/or tunneling in the range below room temperature.