Journal of the Institute of Electronics Engineers of Korea SD
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v.43
no.11
s.353
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pp.37-47
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2006
This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.
These studies were carried out to develop a system for non -destructive and continuous measurement of fresh weight and to analyse the growth response of leaf lettuce under the different nutrient solution and light condition with this system. The developed measurement system was consisted of four load cells and a microcomputer. The output from the system was highly positive correlation with the plant fresh weight above the surface of the hydroponic solution. The top fresh weight of plant could be measured within the error $\pm$ 1.0g in the range of 0 - 2000g. The top fresh weight of leaf lettuce increased 44 times at 18th day after transferring to the nutrient solution, and the maximum growth rate was observed at 13th day after transferring. The growth rate was 10.7- 29.6% per day during 18 days. Optimum concentration of the nutrient solution for the growth of lettuce was 1.4 - 2.2 mS/cm of EC level. When the light condition was changed from dark to light, the fresh weight was temporarily decreased, but the fresh weight increased under the opposite condition. Top fresh weight of leaf lettuce in the darkness normally increased within 12 hours after darkness treatment, and then slowly increased until 78 hours under continuous dark condition. After that times, the fresh weight began to decrease.
In this study, the reactivity of a $SnO_2-ZrO_2$(Sn/Zr = 2/1) catalyst for $SO_2$ reduction by CO was investigated in order to optimize the various reaction conditions such as temperature, gas hourly space velocity (GHSV), and [CO]/[$SO_2$] molar ratio. The reaction temperature in the range of $300{\sim}550^{\circ}C$, space velocity in the range of $5000{\sim}30000cm^3/[g_{-cat}{\cdot}h]$ and [CO]/[$SO_2$] molar ratio in the range of 1.0~4.0 were employed. The optimum temperature, GHSV, and [CO]/[$SO_2$] molar ratio were determined to be $325^{\circ}C$, $10000cm^3/[g_{-cat}{\cdot}h]$, and 2.0, respectively; under these conditions, $SO_2$ conversion was over 99% and sulfur selectivity was over 95%. In addition, the effect of $H_2O$ content on the $SO_2$ reduction by CO was also investigated. As the $H_2O$ content increased from 2 vol% up to 6 vol%, the reactivity and sulfur selectivity decreased. In case of 2 vol% $H_2O$ content, the reaction temperature and [CO]/[$SO_2$] molar ratio were varied in the range of $300{\sim}400^{\circ}C$ and 1.0~3.0. The optimum temperature and [CO]/[$SO_2$] molar ratio were $340^{\circ}C$ and 2.0, respectively under which $SO_2$ conversion and sulfur selectivity were about 90% and 87%, respectively.
Journal of the Institute of Electronics and Information Engineers
/
v.52
no.9
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pp.63-73
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2015
This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.
Journal of the Institute of Electronics and Information Engineers
/
v.53
no.5
/
pp.87-97
/
2016
This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.
In this paper, two schemes of generating reference voltages using enhancement-mode MOS transistors and resistors are proposed. The first one is a voltage-mode scheme where the temperature compensation is made by summing a voltage component proportional to a threshold voltage and a voltage component proportional to a thermal voltage. In the second one, that is a current-mode scheme, the temperature compensation is made by summing a current component proportional to a threshold voltage and a current component proportional to a thermal voltage. The designed circuits have been simulated using a $0.65{\mu}m$ n-well CMOS process parameters. The voltage-mode circuit has a temperature coefficient less than $48.0ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.21%/V for a temperature range of $-30^{\circ}C{\sim}130^{\circ}C$ and a VDD range of $3V{\sim}12V$. The current-mode circuit has a temperature coefficient less than $38.2ppm/^{\circ}C$ and a VDD coefficient less than 0.8%/V for $-30^{\circ}C{\sim}130^{\circ}C\;and\; 4V{\sim}12V$. The power consumption of the voltage-mode and current-mode circuits are $27{\mu}W\;and\;65{\mu}W$ respectively for 5V and $30^{\circ}C$. Measurement results show that the voltage-mode reference circuit has a VDD coefficient less than 0.63%/V for $30^{\circ}C{\sim}100^{\circ}C$ and has a temperature coefficient less than $490ppm/^{\circ}C\;for\;3V{\sim}6V$. The proposed reference circuits are simple and thus easy to design. The proposed current-mode reference circuit can be designed to generate a wide range of reference voltages.
This study was carried out to investigate the interaction of selenate and sulfate ion in nutrient solution supplyed with selenate ion. At early growth stage, the growth of Mongolian wormwood was best at 3mM sulfate ion and 2mg/$\ell$Na$_2$SeO$_4$ treatment. As they were grown and matured, at the later growth stage, the effect of antagonism between selenate and sulfate ion on the growth of each plant decreased. At supplying with selenate ion in nutrient solution, the uptake of selenate by plant had negative correlation with sulfate ion concentration in nutrient solution. The higher sulfate ion concentration, the less selenium uptake. However, the effect of antagonistic interaction of selenate and sulfate ion on the selenium uptake increased with plant age. Whereas, the uptake of sulfate ion had positive correlation with sulfate ion concentration in nutrient solution at supplying with selenate ion in nutrient solution. The uptake of sulfate ion increased with increase of sulfate ion concentration in nutrient solution. The effect of this interaction with selenate and sulfate ion increased with growth and maturity of plant. However, at 3mM sulfate ion concentration in nutrient solution, sulfate ion concentration in plant tissue decreased markedly.
Asia-Pacific Journal of Business Venturing and Entrepreneurship
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v.6
no.3
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pp.109-129
/
2011
Since the introduction of local autonomy system, various specific theories and practical approaches for private commission system have been common concerns and interests of the fields practicing social welfare. In the discussion about private consignment system of social welfare facility and organization, both of private section and government have shown different opinions from various aspects such as related regulation, consignment procedure, proper period and consignment condition. According to the discussion about the consignment system of social welfare facility, the purpose of this study is as follows. The first purpose is to suggest the current status of private consignment of social welfare facility and the characteristic and issue of consignment procedure by considering domestic & overseas literatures about the characteristic of private consignment system. The second purpose is to find out the general characteristics and current statuses of consignment process and system of social welfare facilities (organizations) located in Gyeonggi-do area. The third purpose is to draw the current status and general problem of field consignment system and suggest the practical alternative plan and improvement method of private consignment system of social welfare facility in the future. The result of researching private consignment process by head and manager of social welfare facility (organization), private consignment agreement and its conclusion process and current consignment system improvement method revealed that the number of reconsigned (over 1~3 times) facilities was more than that of initially consigned facilities and senior welfare facility and general social welfare center were most frequent in private consignment organization. In addition, as an improvement method of current private consignment process, the consideration on each organization and standard was required for new consignment and reconsignment and the problem of fairness and objectiveness was indicated when deliberation committee was organized in private consignment process. Besides them, it was found that consignment period shall be adjusted on the basis of facility type and business characteristic and the problems such as worker's succession, worker's transfer and service disconnection were suggested when consignment organization was changed. For conclusion and suggestion, the study suggested the establishment of common standard about private consignment, alternative plan of private consignment process issue and improvement method of consignment period issue.
Park, Kyung Lok;Hong, Sung Wook;Kim, Young Joon;Kim, Soo Jae;Chung, Kun Sub
Microbiology and Biotechnology Letters
/
v.41
no.3
/
pp.327-334
/
2013
For the development of hardy kiwi wine, we arranged for the post-maturity of hardy kiwi fruit, treated them with calcium carbonate and a pectinase enzyme complex, investigated the resulting physicochemical properties and conducted a sensory evaluation. The period determined for creating post-maturity in the hardy kiwi fruit was determined as 5 days storage at room temperature following maturity. During this time the yield of fruit juice was increased from 22.1% to 53.5% using 0.1% (v/v) cytolase PCL5 for 2 h at room temperature. 0.1% (w/v) calcium carbonate was also added during the process of aging, for the reduction of the sour taste. The fermentation trial of the hardy kiwi wine was prepared using water (25% or 50%), sugar ($24^{\circ}brix$), 0.1% (w/v) $CaCO_3$, 0.1% (v/v) cytolase PCL5, $K_2S_2O_5$ (200 ppm), and yeast ($1.5{\times}10^7$ cell/ml). Fermentation then occurred for 2 weeks at $20^{\circ}C$. The pH value, total acidity, alcohol, and reducing sugar content of the resulting hardy kiwi wines of 25% (v/w) and 50% (v/w) water, were in a range of pH 3.4-3.7, 1.12-1.21%, 14.3-14.4%, and 15-16 g/l, respectively. Citric acid and fructose constituted the major organic acids and the free sugar of the 25% and 50% hardy kiwi wine, respectively. Volatile flavor components, including 10 kinds of esters, 8 kinds of alcohols, 5 kinds of acids, 3 kinds of others and aldehydes, were determined by GC analysis. The results of sensory evaluation demonstrated that 50% hardy kiwi wine is more palatable than 25% hardy kiwi wine.
The purpose of this study was to improve the curriculum for industrial design department in the junior colleges. In order to achieve the purpose, two methodologies were carried out. First is job analysis of the industrial designers who have worked in the small & medium manufacturing companies, second is survey for the opinions of professors in the junior colleges. Some results were as follows: 1. The period of junior college for industrial designers is 2 years according to present. But selectively 1 year of advanced course can be established. 2. The practice subjects same as computational formative techniques needed to product development have to be increased. In addition kinds of selection subjects same as foreign language, manufacturing process, new product information and consumer behavior investigation have to be extended. 3. The next subjects need to adjust the title, contents and hours. (1) The need of 3.D related subjects same as computer modeling, computer rendering, 3.D modeling was high. The use of computer is required to design presentation subjects. (2)The need of advertising and sale related subjects same as printing, merchandise, package, typography, photography was low, the need of presentation techniques of new product development was high. (3) The need of field practice, special lecture on practice and reading original texts related subjects was same as at present, but these are not attached importance to form. As the designers feel keenly the necessity of using foreign language, the need of language subject was high.
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