• Journal of the Korean Applied Science and Technology
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• v.29 no.3
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• pp.377-392
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• 2012

It has been known that small solid particles act as a stabilizer in pickering emulsion system. In this study, we successfully prepared stable pickering emulsion in n-hexylalcohol and water system with $TiO_2$ whose surface was treated by alkylsilane. The optimum condition to prepare pickering emulsion stabilized by $TiO_2$ particles was determined by amount of $TiO_2$ particles and ratio of water and oil phase. The type of pickering emulsion was dependent on wettability of particles for water and n-hexylalcohol. When the amount of $TiO_2$ particles increased up to 5.00 wt%, the stability of pickering emulsion was showed to be improved. The most stable pickering emulsion was prepared in the case of W/O type which has the ratio of oil and water phase (3 : 7). We tried to prepare porous $SiO_2-TiO_2$ composite pigments using a pickering emulsion as template at the optimal condition. Porous pigments were synthesized with Ludox HS-30 as an inorganic material by sol-gel process. The characteristics and shape of porous pigments were measured by optical microscope, SEM, BET, XRD and EDS.

• The Journal of the Korea Contents Association
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• v.15 no.9
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• pp.21-28
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• 2015

In the semi-conductor process, a simulation process is performed to detect defects by analyzing the behavior of the impurity through the physical quantity calculation of the inner element. In order to perform the simulation, Finite-Difference Time-Domain(FDTD) algorithm is used. The improvement of semiconductor which is composed of nanoscale elements, the size of simulation is getting bigger. Problems that a processor such as CPU or GPU cannot perform the simulation due to the massive size of matrix or a computer consist of multiple processors cannot handle a massive FDTD may come up. For those problems, studies are performed with parallel/distributed computing. However, in the past, only single type of processor was used. In GPU's case, it performs fast, but at the same time, it has limited memory. On the other hand, in CPU, it performs slower than that of GPU. To solve the problem, we implemented a computing model that can handle any FDTD simulation regardless of size on the cluster which consist of heterogeneous processors. We tested the simulation on processors using MPI libraries which is based on 'point to point' communication and verified that it operates correctly regardless of the number of node and type. Also, we analyzed the performance by measuring the total execution time and specific time for the simulation on each test.

• Journal of the Korean Institute of Landscape Architecture
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• v.41 no.5
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• pp.9-18
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• 2013

Urban parks are public spaces that provide various services for any urban resident to use and enjoy. Parks should be fairly distributed so that the urban parks can be equally used amongst different regions, generations and classes. Researches on spatial distribution of urban parks have been continuously conducted from the past based on the principles of fairness with variety, and it was evident that their techniques have become more elaborate and sophisticated. Yet, there have been limitations in the analysis of residents who are the main users of the urban parks. The research done so far was unable to apply the real number of the residents and it was carried out by only classifying and analyzing the population by the same scale(grid in the same sizes), postal(zip) code and administrative district. The actual population that resides within the usable range of urban parks was not used. This study analyzes and evaluates the spatial distribution that the residents can use on foot, by utilizing the service areas and the residents' registration data by addresses. In this study, to analyze the square measure of the service areas of neighborhood parks in Daegu Metropolitan City and the number of residents within and outside of the service area, network analysis techniques were employed and the residents' registration data were utilized. Major findings were that the Square measure of service areas of neighborhood parks turned out to be 31.23% of the square measure of the residential areas and also, that only 43.03% of the population of the Daegu Metropolitan area lives within the service areas of the neighborhood parks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.635-639
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• 2016

In the devices used in the microwave frequency band, the gain decreases as the frequency increases due to the parasitic component. To compensate for these characteristics, a linear gain equalizer with an opposite slope is needed in wideband systems, such as those used for electronic warfare. In this study, a linear gain equalizer that can be used in the 18 ~ 40GHz band is designed and fabricated. Circuit design and momentum design (optimizations) were carried out to reduce the errors between design and manufacturing. A thin film process is used to minimize the parasitic components within the implementation frequency band. A sheet resistance of 100 ohm/square was employed to minimize the wavelength variation due to the length of the thin film resistor. This linear gain equalizer is a structure that combines a quarter wavelength-resonator on a series microstrip line with a resistor. All three 1/4 wavelength short resonators were used. The fabricated linear gain equalizer has a loss of more than -5dB at 40GHz and a 6dB slope in the 18 ~ 40GHz band. By using the manufactured gain equalizer in a multi-stage connected device such as an electronic warfare receiver, the gain flatness degradation with increasing frequency can be reduced.

• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.545-554
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• 2003

Design of the optical modulator composed of a three-waveguide coupler and CPW traveling-wave electrodes was carried out. Switching phenomena of three-waveguide couplers were analyzed by using the coupled mode theory, and the coupling-lengths of the devices were calculated by means of the FDM. CPW traveling-wave electrodes were analysed by the CMM and SOR simulation technique in order to find the conditions of phase-velocity and impedance matching. Traveling-wave modulators were fabricated on z-cut LiNbO$_3$ substrate. Ti was in-diffused in LiNbO$_3$ to make waveguides and Au electrodes were built on the waveguides by the electrolyte technique. The fabricated modulator chip was end-polished, pig-tailed and packaged in a brass mount with K-connector. The insertion loss and the switching voltage of the optical modulator were about 4㏈ and 19V, respectively. Network analyzer was used to obtain the S parameter and the corresponding RF response. From the measurement, parameters of the traveling-wave electrodes were extracted to be Z$_{c}$= 45 Ω, N$_{eff}$=2.20, and $\alpha$$_{0}$=0.055/cm√GHZ. The measured optical response R($\omega$) was compared with the theoretically estimated one, showing both responses agree well. The measurement results revealed that 3㏈ bandwidth turned out to be about 13 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.27-36
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• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.735-741
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• 2016

Increasing the total length of waveguide-below-cutoff array(WBCA) as it is used to the duct in order to enhance shielding effectiveness, the design could cause higher cost, higher levels of difficulties in construction and the interruption a flow velocity. The multi-layered WBCA can compensate for this problem, which can be designed by crossing each waveguide layer. By conducting simulations from 2-layer to 8-layer structure, it can be observed that the shielding effectiveness increases from 52 dB to 75 dB. Comparing with the original WBCA in a shape of mono layer rectangular, our proposed waveguide becomes similar with the original value as the number of crossing layer increases. In addition, the analysis with the flow of fluid in the duct installed multi-layered WBCA are required. We demonstrate this analysis by doing the flow of fluid simulation, and concluded that the multi-layered WBCA has loss of flow of fluid less than unit rectangular WBCA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.