• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.105.2-105.2
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• 2010

전처리 후 얻어진 셀룰로스 고분자를 단당류로 전환하기 위해서는 셀룰라제를 이용한 당화 과정이 필요하다. 통상 실험식 연구에서는 셀룰로스 당화시 당수율을 최대로 하기위해 pH조절을 위한 Citrate buffer와 미생물 오염을 막기 위한 Autoclave에서의 멸균 과정을 거친다. 하지만 대량생산을 목적으로 하는 산업체에서는 적용이 어렵다는 문제점이 있다. 따라서 본 연구에서 이를 대신하여 산업체에서 적용 가능한 당화전환 공정의 효율성을 평가하고자 하였다. Autoclave 멸균을 대체하는 공정으로 항생제 첨가와 여과에 의한 제균을 선택하였고, citrate buffer를 대신하여 buffer를 첨가하지 않은 물을 pH를 조정하여 사용 하였다.실험결과 기존의 당화공정을 사용하였을 때 당화율이 81%이었고, pH를 조절한 제균 water에 항생제를 첨가하는 공정은 71%로 나머지 배지들 중 가장 높은 당화율을 나타냈다. 이것은 기존의 당화율보다 10% 낮은 수치이나 공정비를 교려하여 봤을 때 효율성 있는 공정으로 판단된다.

• ETRI Journal
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• v.10 no.4
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• pp.33-39
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• 1988

본 고는 자기동조 제어기 구성에 관한 논문으로 제어기는 공정의 매개변수 변화와 외란, 잡음에 대하여 운용자의 조작없이 스스로 제어 특성을 만족하도록 동작하며, 공장자동화 시스팀의 일부로서 계층제어 시스팀 구성이 가능한 통신기능을 가지고 있다. 또한, 공정의 시간지연, 불감시간, 비선형 등에 대해서 만족할만한 제어효과를 나타내며, 범용자기동조 제어모드와 PID제어모드를 갖는다. 본문에서는 자기동조 제어기의 시스팀구성, 하드웨어구성, 소프트웨어구성에 대하여 기술한다.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.85-90
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• 2002

In the construction industry, projects are becoming increasingly large and complex, involving multiple subcontractors. Traditional centralized coordination techniques used by the general contractors become less effective as subcontractors perform most work and provide their own resources. When subcontractors cannot provide enough resources, they hinder their own performance as well as that of other subcontractors and ultimately the entire project. Thus, construction projects need a new distributed coordination approach wherein all of the concerned subcontractors can reschedule a project dynamically. To enable the new distributed coordination of project schedule changes, I developed a novel agent-based compensatory negotiation methodology, which allows software agents to simulate negotiations on behalf of their human subcontractors. This research formalizes the necessary steps that would help construction project participants to increase the efficiency of their resource use, which in turn will enhance successful completions of whole projects.

• Korean Journal of Construction Engineering and Management
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• v.5 no.1 s.17
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• pp.124-132
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• 2004

A human resource management of the general contractors is to mostly deal with daily input by each subcontractor in construction fields. However, this way has some limitations; the identification of proper human-input and productivity, preventive activities or efforts for minimizing schedule delay. The reason why these limitations are that few systematic efforts through a coordinated field administration with the construction schedule planning and human resources. Therefore, on the basis of the construction schedule planning, human resource management of subcontractors is necessary to make for an improvement in construction schedule control. Daily Scheduling Check System(DSCS), as the linked human resources on an existed CPM scheduling software, was developed and this paper then verified validity and effectiveness of using the DSCS for the framework of some actual apartment construction projects

• Membrane Journal
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• v.31 no.4
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• pp.253-261
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• 2021

Solutions to water pollution, global warming, and climate change have been currently discussed. Pressure retarded osmosis (PRO) using a difference in salt concentration between two fluids is proposed to meet the demand for clean water and produce eco-friendly energy. Although PRO has been researched continuously, it has not been commercialized yet due to limitations such as lack of technology and the high price of membranes. Meanwhile, the membrane is one of the most significant parts of the PRO engine and salinity gradient power (SGP) technology. Research continues to technologically develop graphene oxide membranes and nanocomposite membranes used in salinity gradient power generation. Studies on efficient membranes, solvents, and solutes are active to enable high energy efficiency of the osmotic heat engine even at low temperatures of waste. Studies have been conducted on reducing internal concentration polarization and increasing power density by using membranes with balanced permeability and selectivity. In this review, dealing with these studies, we discuss the types of PRO membranes, theoretical modeling of technologies through efficient membranes, and other technologies to develop the process efficiency.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.249-256
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• 2007

GPS(generalized processor sharing) is a fair scheduling scheme that guarantees fair distribution of resources in an instantaneous manner, while virtual clock pursues fairness in the sense of long-term. In this paper, we notice that the degree of memorylessness is the key difference of the two schemes, and propose a unified scheduling model that covers the whole spectrum of history-sensitiveness. In this model, each application's resource right is represented in a value called deposit, which is accumulated at a predefined rate and is consumed for services. The unused deposit, representing non-usage history, gives the application more opportunity to be scheduled, hence relatively enhancing its response time. Decay of the deposit means partial erase of the history and, by adjusting the decaying rate, the degree of history-sensitiveness is controlled. In the spectrum, the memoryless end corresponds GPS and the other end with full history corresponds virtual clock. And there exists a tradeoff between average delay and long-term fairness. We examine the properties of the model by analysis and simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• The KIPS Transactions:PartA
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• v.17A no.1
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• pp.27-32
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• 2010

Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2007.11a
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• pp.805-808
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• 2007

Recently there are many contract claims, which are caused by duration delay, in construction industry. Many kinds of research for solving such duration delay problem are being progressed and an effective computerized system needs to improve it. This study suggests an improved methodology and necessary functions to make a time impact analysis system. This results will be useful for quantifying responsible number of days caused by duration delay.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.924-927
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• 2017

This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.