• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.1-10
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• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.25 no.6
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• pp.469-476
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• 2012

In this paper, a finite element domain decomposition method using local and mixed Lagrange multipliers for a large scal structural analysis is presented. The proposed algorithms use local and mixed Lagrange multipliers to improve computational efficiency. In the original FETI method, classical Lagrange multiplier technique was used. In the dual-primal FETI method, the interface nodes are used at the corner nodes of each sub-domain. On the other hand, the proposed FETI-local analysis adopts localized Lagrange multipliers and the proposed FETI-mixed analysis uses both global and local Lagrange multipliers. The numerical analysis results by the proposed algorithms are compared with those obtained by dual-primal FETI method.

• The KIPS Transactions:PartA
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• v.11A no.3
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• pp.199-206
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• 2004

Under the multiprogrammed situation, the performance of multiprocessor system is affected by the process allocation policy of the operating systems. The lowest communication cost can be achieved when the related processes positioned to the adjacent processors. While the effective allocation is quite difficult to the real situation, and the processing of the allocation policy consumes some computation time. The dual-ring CC-NUMA systems exhibit a quite performance difference according to the process a1location policy due to a lot of unbalanced memory transactions on the interconnection networks. In this paper, I propose a load balanced dual-link CC-NUMA system that does not requires the processes allocation policy. By the program-driven simulation results. the proposed system shows no remarkable difference according to the allocation policy while the dual-ring systems shows 10％ performance improvement by the process allocation. In addition, the proposed system outperforms the dual~ring systems about 1.5 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.358-360
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• 2005

현재 RFID 네트워크의 구조적 기준이 되는 EPC Network는 HTTP/SOAP 통신 프로토콜과 HTML/XML를 이용하여 서비스를 제공하지만, 이동 RFID 네트워크에서는 핸드폰의 메모리 배터리가 가지는 제약성과 대역폭이 작은 무선 환경에 따른 문제로 인해 WAP 통신 프로토콜과 경량의 WML를 사용한다. 이에 본 논문에서는 두 네트워크간의 프로토콜 변환과 데이터포맷 변환을 통해 상호 정보교환 및 공유 문제에 대한 해결방안을 제시한다. EPC 네트워크에서 제공하는 서비스인 IS(Information Service), DS(Discovery Service) 서비스와 이동 RFID 네트워크 U에서 리더가 부착된 핸드폰(Radio Frequency Mobile Station : RFMS)로 이용하게 될 IS, DS 서비스간의 연동 시 제기되는 가장 대표적 문제점인 표현방법과 통신 프로토콜의 차이의 해결을 위해 EPC-Proxy를 두어 그 안에서 EPC-Proxy의 정확한 기능 역할 및 동작과 이동 RFID 네트워크가 관할하는 RFID 태그에 대해서 이동 RFID 네트워크의 local ONS가 가져야 할 NAPTR RR 정보를 통한 EPC 네트워크와 이동 RFID 네트워크의 서비스 호환 및 상호운용 방식을 제시한다.

• Proceedings of the KIEE Conference
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• 2004.11b
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• pp.151-154
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• 2004

본 논문에서는 IEEE123 모선 배전계통에 분산전원 투입이 가능하도록 GUI 조류계산프로그램 개발하였다. 첫째로 제안된 배전용 조류계산 프로그램은 기존의 배전용 조류계산의 한계를 벗어나 분산전원을 투입을 가능하게 하고 비주얼하게 온라인으로 배전계통의 구조를 컴퓨터 마우스 클릭으로 손쉽게 할 수 있도록 구성하였다. 둘째로 GUI부분에서 모선, 선로, 차단기의 정보를 표시할 수도 있고 사용자가 분산전원의 투입이나 차단 그리고 선로 및 부하의 투입 및 차단이 가능하도록 하였다. 개발된 프로그램은 데이터 변환기, 조류계산프로그램 및 GUI로 구성되어 있으며 이 3부분은 메시지 Queue 명령에 의하여 서로 메모리를 공유하도록 되어있다. 분산전원 투입 및 차단은 4군데로 지정하여 분산전원 투입량의 효과를 시각적으로 표시하는 데 편하도록 되어 있다. 조류계산의 결과는 GUI상에 유효전력, 무효전력, 모선전압, 역률을 각 모선의 근접 위치에 나타낸다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.