• Journal of Advanced Navigation Technology
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• v.13 no.2
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• pp.238-243
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• 2009

Now, the production process systems are largely based on automatic system using the wired network. The production process systems using wired network has disadvantage that it is expensive when the installed and replaced equipment. The each equipment happens to repair cost for control and management in production processes. And the replaced equipment has also the additional expense and breaks production process. These problems are solved through wireless communication between the industrial equipments. So, we propose wireless production process system based on IEEE 802.15.4 technology. It solves a complicated space and stops by replaced equipment in the factory. Then we simulated and analyzed IEEE 802.15.4 for Industrial Equipment based on Wireless Network.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5801-5812
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• 2014

The retention basin is a hydraulic structure for flood mitigation by storing river flow over a design flood. In this study, numerical models were adopted to simulate the flood mitigation effects by a retention basin. The large flood condition was applied as a boundary condition to consider an abnormal flood caused by climate change. Furthermore, the two-dimensional numerical model was adopted to regenerate the complex flow pattern due to the topography and lateral flow near the retention basin. The numerical results of the one- and two-dimensional model were analyzed and compared. The results showed that the two-dimensional model is more applicable to assessing flood mitigation by the retention basin with a complex topography and lateral flow patterns.

• Journal of KIISE:Software and Applications
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• v.30 no.3_4
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• pp.251-258
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• 2003

A support vector machine (SVM) is supposed to provide a good generalization performance, but the actual performance of a actually implemented SVM is often far from the theoretically expected level. This is largely because the implementation is based on an approximated algorithm, due to the high complexity of time and space. To improve this limitation, we propose ensemble of SVMs by using Bagging (bootstrap aggregating) and Boosting. By a Bagging stage each individual SVM is trained independently using randomly chosen training samples via a bootstrap technique. By a Boosting stage an individual SVM is trained by choosing training samples according to their probability distribution. The probability distribution is updated by the error of independent classifiers, and the process is iterated. After the training stage, they are aggregated to make a collective decision in several ways, such ai majority voting, the LSE(least squares estimation) -based weighting, and double layer hierarchical combining. The simulation results for IRIS data classification, the hand-written digit recognition and Face detection show that the proposed SVM ensembles greatly outperforms a single SVM in terms of classification accuracy.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.3
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• pp.170-182
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• 2006

Last few years have seen a rapid increase in research on ubiquitous computing. Ubiquitous computing is often touted as a technology that will make computing available to the user anywhere and anytime. One important problem to be addressed in building such a ubiquitous computing environment is how to manage services and deliver them to the user in an effective manner. This paper presents our model called Personal Kiosk(PK) as a way of solving the problem. PK is a model of ubiquitous service provisioning that enables the user to use desired services anytime and anywhere. The design and implementation of the current PK in the 'Local Area' setting with related technical issues are also presented. A location-sensing technique for indoor users and a personalized service provisioning based on user location and privileges are discussed in detail.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.10-18
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• 2004

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The operations of unaligned linear quadtrees, which are operations among the linear quadtrees with different origin, are able to perform the translated or rotated images efficiently. And this operations requires alignment of the linear quadtrees. In this paper, we present an efficient algorithm to perform alignment of unaligned linear quadtrees, using three-dimensional $n{\pm}n{\pm}n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of $n{\pm}n{\pm}n$ RMESH.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.1-9
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• 2004

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations using a binary method, while division and inversion can be performed by the iterative application of an AB$^2$ operation. Hence, it is important to develop a fast algorithm and efficient hardware for this operations. In this paper presents new bit-serial architectures for the simultaneous computation of multiplication and squaring operations, and the computation of an $AB^2$ operation over $GF(2^m)$ generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the Proposed architectures include regularity and modularity, they can be easily designed on VLSI hardware and used in IC cards.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.549-557
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• 2016

It is important for effective visualization to summarize not only a large amount of debugging information but also the mental models of abstract ideas. This paper presents an abstract visualization tool which provides effective visualization of thread structure and race information for OpenMP programs with critical sections and nested parallelism, using a partial order execution graph which captures logical concurrency among threads. This tool is supported by an on-the-fly trace-filtering technique to reduce space complexity of visualization information, and a graph abstraction technique to reduce visual complexity of nested parallelism and critical sections in the filtered trace. The graph abstraction of partial-order relation and race information is effective for understanding program execution and detecting to eliminate races, because the user can examine control flow of program and locations of races in a structural fashion.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.357-368
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• 2003

Evaluation of shape similarity for 3D models is essential in many areas - medicine, mechanical engineering, molecular biology, etc. Moreover, as 3D models are commonly used on the Web, many researches have been made on the classification and retrieval of 3D models. In this paper, we describe methods for 3D shape representation and major concepts of similarity evaluation, and analyze the key features of recent researches for shape comparison after classifying them into four categories including multi-resolution, topology, 2D image, and statistics based methods. In addition, we evaluated the performance of the reviewed methods by the selected criteria such as uniqueness, robustness, invariance, multi-resolution, efficiency, and comparison scope. Multi-resolution based methods have resulted in decreased computation time for comparison and increased preprocessing time. The methods using geometric and topological information were able to compare more various types of models and were robust to partial shape comparison. 2D image based methods incurred overheads in time and space complexity. Statistics based methods allowed for shape comparison without pose-normalization and showed robustness against affine transformations and noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.278-286
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• 2007

In this paper, an efficient algorithm is proposed for the interpolation of interlaced images. First of all, by efficiently estimating the directional spatial correlations of neighboring pixels, increased interpolation accuracy can be achieved. And then using the gradient vector which was obtained by Sobel operation, enables to consider the fine directional edges and make it possible to estimate the accurate direction of edges. In other words, it is possible to interpolate the interlaced images with considering the characteristics of images. In addition, by altering the conventional edge detector for the purpose of a easy De-interlacing and multiplying the optimal translation coefficients to each of the gradient vectors, an efficient interpolation for images can be achieved. Comparing with the conventional De-interlacing algorithms, proposed algorithm not only reduced the complexity but also estimated the accurate edge direction and the proposed scheme have been clearly verified that it enhances the objective and subjective image quality by the extensive simulations for various images.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.119-124
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• 1998

Block Matching Motion Estimation(BMME) Algorithm is demands a very large amount of computing power and have been proposed many fast algorithms. These algorithms are many problem that larger size of VLSI scale due to non-localized search block data and problem of non-reuse of input data for each processing step. In this paper, we designed systolic arry of high processing capacity, constraints input output pin size and reuse of input data for small VLSI size. The proposed systolic array is optimized memory access time because of iterative reuse of input data on search block and become independent of problem size due to increase of algorithm's parallelism and total processing elements connection is localized spatial and temporal. The designed systolic array is reduced O(N6) time complexity to O(N3) on moving vector and has O(N) input/output pin size.