• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1217-1224
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• 2003

In this paper, we propose an edge side-lobe suppressor (ESS) for the uplink of OFDMA systems, which mitigates the interference introduced by different frequency offsets between a desired user and the other users. We evaluate the proposed ESS scheme by measuring average signal to interference ratio (SIR) and average bit error rate (BER). The simulation results confirm that the proposed ESS scheme improves system performance by approximately 5∼10 dB SIR as compared to conventional OFDMA systems. Because the additional operations for the proposed scheme can be performed by a real-valued look-up table, the implementation of the ESS hardly requires increasing transmitter and receiver complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.777-784
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• 2004

In this paper, a new filter structure to improve frequency response characteristics in decimation filter using CIC(Cascaded Integrator-Comb) filters and half band filters is proposed. Conventional filters improve only passband characteristics, but we propose a new filter which can improve stop band and pass band characteristics simultaneously. Since proposed filter needs only two multiplication, additional implementation cost is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, filter coefficients quantization effects ate discussed after Verilog-HDL coding.

• Journal of Broadcast Engineering
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• v.1 no.2
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• pp.108-117
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• 1996

In this paper we propose a Wavelet- based compression algorithm of HDTV video signals for the purpose of recording HDTV signals in the digital VTR. Comparing to the DCT- based compression method, which only yields unrecognizable DCT coefficients, the low frequency components of Wavelet coefficients maintain recognizable spatial domain information. So, it is more suitable for various VTR operations such as editing and multi-speed mode operations. Also, the adopted Wavelet filter can be Implemented with simple shift operations, which can reduce the computational complexities substantially. The quality of reconstructed HDTV signals with a 4:1 compression ratio turns out to be good enough for the studio use.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.683-690
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• 2015

Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.306-313
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• 2007

In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.99-106
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• 2004

In this Paper, the matched filter for searching initial synchronization in DSSS (direct sequence spread spectrum) receiver is studied. The matched filter with a single data flow path is described which can be presented by HDL (Hardware Description Language). In order to improve the processing time of operations for the filter, equations are arranged to represent two data flow paths and the associated hardware model is proposed. The model has an architecture based on parallelism and pipeline for fast processing, in which two data flow paths with a series of memory, multiplier and accumulator are placed in parallel. The performance of the model is analyzed and compared with the matched filter with a single data flow path.

• The Mathematical Education
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• v.51 no.1
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• pp.21-45
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• 2012

The purpose of the study was to investigate how students understand each operations with whole numbers and fractions, and the relationship between their knowledge of operations with whole numbers and conceptual understanding of operations on fractions. Researchers categorized students' understanding of operations with whole numbers and fractions based on their semantic structure of these operations, and analyzed the relationship between students' understanding of operations with whole numbers and fractions. As the results, some students who understood multiplications with whole numbers as only situations of "equal groups" did not properly conceptualize multiplications of fractions as they interpreted wrongly multiplying two fractions as adding two fractions. On the other hand, some students who understood multiplications with whole numbers as situations of "multiplicative comparison" appropriately conceptualize multiplications of fractions. They naturally constructed knowledge of fractions as they build on their prior knowledge of whole numbers compared to other students. In the case of division, we found that some students who understood divisions with whole numbers as only situations of "sharing" had difficulty in constructing division knowledge of fractions from previous division knowledge of whole numbers.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.2
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• pp.17-25
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• 2003

In this paper, a processor architecture is proposed based on the state space implementation technique for real time processing of 2-D discrete wavelet transform(DWT). It conducts 2-D DWT operations in consideration of row and column direction simultaneously, thus can reduce latency due to memory access for storing intermediate results. It is a VLSI architecture suitable for real time processing. The proposed architecture includes only four multipliers and four adders, and NK-N internal memory storage, where K denotes the length of filter. It has a small hardware complexity. Therefore it is very suitable architecture for real time, embedded applications such as web camera server. Since the processor is easily extended to array structure, it can be applied to various image processing applications.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.5
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• pp.368-374
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• 2016

This paper presents an experimental study on an electrical circuit model of the TiO2-based nano-wired memristor device for neuromophic applications. The electrical circuit equivalent model of the proposed memristor device consists of several electronics components and some passive devices including operational amplifiers, multipliers, resistors and capacitors. In order to verify the proposed design, both of simulation (using PSPICE) as well as hardware implementation were performed for the analysis of the memristor circuit with time waveforms, frequency spectra, I-V curves and power curves. The gained results from the measured data showed a good agreement with the simulation result that confirm the proposed idea.