• Journal of Broadcast Engineering
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• v.17 no.1
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• pp.195-198
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• 2012

The N basis functions are typically chosen so that Surface reflectance functions(SRFs) and spectral power distributions (SPDs) can be accurately reconstructed from their N-dimensional vector codes. Typical rendering applications assume that the resulting mapping is an isomorphism where vector operations of addition, scalar multiplication, component-wise multiplication on the N-vectors can be used to model physical operations such as superposition of lights, light-surface interactions and inter-reflection. The vector operations do not mirror the physical. However, if the choice of basis functions is restricted to characteristic functions then the resulting map between SPDs/SRFs and N-vectors is anisomorphism that preserves the physical operations needed in rendering. This paper will show how to select optimal characteristic function bases of any dimension N (number of basis functions) and also evaluate how accurately a large set of Munsell color chips can approximated as basis functions of dimension N.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.1
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• pp.33-43
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• 2023

The National Institute of Standards and Technology (NIST), which is working on the Post-Quantum Cryptography (PQC) standardization project, announced four algorithms that have been finalized for standardization. In this paper, we demonstrate through experiments that private keys can be exposed by Correlation Power Analysis (CPA) and Differential Deep Learning Analysis (DDLA) attacks on polynomial coefficient-wise multiplication algorithms that operate in the process of generating signatures using CRYSTALS-Dilithium algorithm. As a result of the experiment on ARM-Cortex-M4, we succeeded in recovering the private key coefficient using CPA or DDLA attacks. In particular, when StandardScaler preprocessing and continuous wavelet transform applied power traces were used in the DDLA attack, the minimum number of power traces required for attacks is reduced and the Normalized Maximum Margines (NMM) value increased by about 3 times. Conseqently, the proposed methods significantly improves the attack performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.651-654
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• 2008

In finite field operations based on $GF(2^m)$, additions and subtractions are easily implemented. On the other hand, multiplications and divisions require mathematical elaboration of complex equations. There are two dominant way of approaching the solutions of finite filed operations, normal basis approach and polynomial basis approach, each of which has both benefits and weakness respectively. In this study, we adopted the mathematically feasible polynomial basis approach and suggest the optimization techniques of finite field operations based of mathematical principles.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.813-816
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• 2005

In last several years, the need for the right of privacy and mobile banking has increased. The RSA system is one of the most widely used public key cryptography systems, and its core arithmetic operation IS modular multiplication. P. L. Montgomery proposed a very efficient modular multiplication technique that is well suited to hardware implementation. In this paper, the montgomery modular multiplication algorithms(CIOS, SOS, FIOS) , developed by Cetin Kaya Koc, is presented and implemented using radix-16 and Altera FPGA. Also, we undertake comparisons of power dissipation using Quatrus II PowerPlay Power Analyzer.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.255-258
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• 2000

본 논문에서는 효율적인 면적의 저전력 FIR 필터를 제안한다. 제안된 필터는 6 비트 8 탭의 구조를 갖는PRML(Partial-Response Maximum Likelihood) 디스크드라이브 read channel용 FIR 필터이다 제안된 구조는 병렬연산 구조를 채택하고 있으며 네 단의 파이프라인 구조를 가지고 있다. 곱셈을 위하여 부스 알고리즘이 사용되며 압축기를 이용하여 덧셈을 수행한다. 저전력을 위해 CMOS 패스 트랜지스터를 사용하였으며 면적을 줄이기 위해 single-rail 로직을 사용하였다 제안된 구조를 0.65㎛ CMOS 공정을 이용하여 설계하였으며1.88 × 1.38㎟의 면적을 차지하였고 HSPICE 시뮬레이션 결과 3.3V의 공급전압에서 100㎒로 동작시 120㎽의 전력을 소모한다. 제안된 구조는 기존의 구조들에 비해 약 11%의 전력이 감소했으며 약 33%의 면적이 감소하였다.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.356-360
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• 2006

Recently, many power analysis attacks have been proposed. Since the attacks are powerful, it is very important to implement cryptosystems securely against the attacks. We propose countermeasures against power analysis attacks for elliptic curve cryptosystems based on Koblitz curves (KCs), which are a special class of elliptic curves. That is, we make our countermeasures be secure against SPA, DPA, and new DPA attacks, specially RPA, ZPA, using a random point at each execution of elliptic curve scalar multiplication. And since our countermeasures are designed to use the Frobenius map of KC, those are very fast.

• Journal of Institute of Convergence Technology
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• v.9 no.1
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• pp.1-6
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• 2019

Matrix multiplication is a fundamental mathematical operation that has numerous applications across most scientific fields. In this paper, we presents a parallel GPU computation algorithm for dense matrix-matrix multiplication using OpenGL compute shader, which can play a very important role as a fundamental building block for many high-performance computing applications. Experimental results on NVIDIA Quad 4000 show that the proposed algorithm runs about 208 times faster than previous CPU algorithm and achieves performance of 75 GFLOPS in single precision for dense matrices with matrix size 4,096. Such performance proves that our algorithm is practical for real applications.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2967-2969
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• 2005

2003년에 영상압축의 표준으로 제시된 H.264/AVC의 압축성능은 대부분 Context-based Adaptive Binary Arithmetic Codes (CAHAC)라는 새로운 엔트로피 코딩에 기인한 것이다. 그러나, CABAC의 뛰어난 성능에도 불구하고 복잡한 처리과정 때문에 하드웨어로 구현하기가 상당히 곤란하다. 곱셈기가 없는 알고리즘임에도 불구하고 영역(range), 오프셋(offset), 그리고 컨텍스트 변수들(context varivales)을 순차적으로 구해야 하기 때문이다. 이 논문에서는 한번에 최대 두 비트를 디코딩 할 수 있는 예측기법을 통하여 CARAC의 전체적인 디코딩 시간을 줄일 수 있는 방법을 제안한다. 한 비트를 디코딩하기 위해서는 두 개의 심볼(a set of binary symbols)에 대한 확률분포를 사전에 알아야 하지만, 제안된 방법에서는 두 비트를 동시에 디코딩할 수 있도록 네 개의 심볼(two sets of binary symbols)에 대한 확률 분포를 예측하여 디코더에 제공한다. 제안된 예측기법을 CABAC 디코더에 적용한 결과, 기존보다 10-13%의 복호시간을 단축하는 효과를 가졌다. 논문에서 제안된 예측기법을 통한 고속디코더의 구현은 확률을 기반으로 하는 신호처리에 사용되어 고속의 시스템을 구성하는데 효과적으로 적용될 수 있다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.429-430
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• 2008

FFT(Fast Fourier Transform)는 멀티미디어 통신 및 디지털 신호처리 분야, 특히 무선통신이나 디지털 방송 등에서 쓰이는 OFDM(Orthogonal Frequency Division Multiplexing)에서 필수적인 역할을 하고 있다. 본 논문에서는 파이프라인 FFT 프로세서 설계의 다양한 알고리즘 및 하드웨어 구조에 대해 살펴보고 이를 한 눈에 파악할 수 있는 설계 가이드라인을 제시한다. 또한 분석 중 Radix-2 Single-path Delay Feedback의 복소곱셈기의 비효율적인 면을 찾고 새로운 R2SDF 구조를 제안한다.