• Title/Summary/Keyword: 곱셈 구조

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Design of $AB^2 $ Multiplier for Public-key Cryptosystem (공개키 암호 시스템을 위한 $AB^2 $곱셈기 설계)

  • 김현성;유기영
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.2
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    • pp.93-98
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    • 2003
  • This paper presents two new algorithms and their architectures for $AB^2 $ multiplication over $GF(2^m)$.First, a new architecture with a new algorithm is designed based on LFSR (Linear Feedback Shift Register) architecture. Furthermore, modified $AB^2 $ multiplier is derived from the multiplier. The multipliers and the structure use AOP (All One Polynomial) as a modulus, which hat the properties of ail coefficients with 1. Simulation results thews that proposed architecture has lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponential ion architecture, which is the tore operation In public-key cryptosystems.

Teaching Multiplication with Whole Numbers in Elementary School Mathematics -Focusing on the Introduction of the Concept of Multiplication and Multiplication Facts- (초등수학에서 자연수 곱셈 지도 -곱셈의 도입과 곱셈 구구를 중심으로-)

  • Chong, Yeong Ok
    • School Mathematics
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    • v.15 no.4
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    • pp.889-920
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    • 2013
  • The aim of this study is to look into the didactical background for introducing the concept of multiplication and teaching multiplication facts in elementary school mathematics and offer suggestions to improve teaching multiplication in the future. In order to attain these purposes, this study deduced and examined concepts of multiplication, situations involving multiplication, didactical models for multiplication and multiplication strategies based on key ideas with respect to the didactical background on teaching multiplication through a theoretical consideration regarding various studies on multiplication. Based on such examination, this study compared and analyzed textbooks used in the United States, Finland, the Netherlands, Germany and South Korea. In the light of such theoretical consideration and analytical results, this study provided implication for improving teaching multiplication in elementary schools in Korea as follows: diversifying equal groups situations, emphasizing multiplicative comparison situations, reconsidering Cartesian product situations for providing situations involving multiplication, balancing among the group model, array model and line model and transposing from material models to structured and formal ones in using didactical models for multiplication, emphasizing multiplication strategies and properties of multiplication and connecting learned facts and new facts with one another for teaching multiplication facts.

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Cellular Automata based on VLSI architecture over GF($2^m$) (GF($2^m$)상의 셀룰라 오토마타를 이용한 VLSI 구조)

  • 전준철;김현성;이형목;유기영
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.3
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    • pp.87-94
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    • 2002
  • This study presents an MSB(Most Significant Bit) Int multiplier using cellular automata, along with a new MSB first multiplication algorithm over GF($2^m$). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of a PBCA(Periodic Boundary Cellular Automata) and with the property of irreducible AOP(All One Polynomial). The proposed multiplier can be used in the effectual hardware design of exponentiation architecture for public-key cryptosystem.

The Analysis of Proportional Reasoning Tasks in Elementary School Mathematics Textbooks (초등학교 수학 교과서에 제시된 비례추론 과제의 분석)

  • Song, Dong Hyun;Park, Young Hee
    • Education of Primary School Mathematics
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    • v.25 no.1
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    • pp.57-79
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    • 2022
  • Current mathematics It is necessary to ensure that ratio and proportion concept is not distorted or broken while being treated as if they were easy to teach and learn in school. Therefore, the purpose of this study is to analyze the activities presented in the textbook. Based on prior work, this study reinterpreted the proportional reasoning task from the proportional perspective of Beckmann and Izsak(2015) to the multiplicative structure of Vergnaud(1996) in four ways. This compared how they interpreted the multiplicative structure and relationships between two measurement spaces of ratio and rate units and proportional expression and proportional distribution units presented in the revised textbooks of 2007, 2009, and 2015 curriculum. First, the study found that the proportional reasoning task presented in the ratio and rate section varied by increasing both the ratio structure type and the proportional reasoning activity during the 2009 curriculum, but simplified the content by decreasing both the percentage structure type and the proportional reasoning activity. In addition, during the 2015 curriculum, the content was simplified by decreasing both the type of multiplicative structure of ratio and rate and the type of proportional reasoning, but both the type of multiplicative structure of percentage and the content varied. Second, the study found that, the proportional reasoning task presented in the proportional expression and proportional distribute sections was similar to the previous one, as both the type of multiplicative structure and the type of proportional reasoning strategy increased during the 2009 curriculum. In addition, during the 2015 curriculum, both the type of multiplicative structure and the activity of proportional reasoning increased, but the proportional distribution were similar to the previous one as there was no significant change in the type of multiplicative structure and proportional reasoning. Therefore, teachers need to make efforts to analyze the multiplicative structure and proportional reasoning strategies of the activities presented in the textbook and reconstruct them according to the concepts to teach them so that students can experience proportional reasoning in various situations.

New Multiplier using Montgomery Algorithm over Finite Fields (유한필드상에서 몽고메리 알고리즘을 이용한 곱셈기 설계)

  • 하경주;이창순
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 2002.06a
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    • pp.190-194
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    • 2002
  • Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.

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Implementation of a LSB-First Digit-Serial Multiplier for Finite Fields GF(2m) (유한 필드 GF(2m)상에서의 LSB 우선 디지트 시리얼 곱셈기 구현)

  • Kim, Chang-Hun;Hong, Chun-Pyo;U, Jong-Jeong
    • The KIPS Transactions:PartA
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    • v.9A no.3
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    • pp.281-286
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    • 2002
  • In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

Implementation of Hilbert Transformer using Fixed-Width Multiplier (고정길이 곱셈기를 이용한 Hilbert Transformer 구현)

  • 조경주;김명순;유경주;정진균
    • Proceedings of the IEEK Conference
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    • 2001.09a
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    • pp.861-864
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    • 2001
  • 많은 멀티미디어와 DSP 응용에서 입력과 출력 데이터 길이가 같은 고정 길이 곱셈기가 요구된다. 고정 길이 곱셈기는 확률적인 추정에 근거한 적절한 보상 바이어스를 더해줌으로써 일반적인 병렬 곱셈기와 비교하여 50%의 면적을 줄일 수 있다. 본 논문에서는 CSD 곱셈기에 적합한 고정길이 곱셈기의 구조를 제시하고 전파 캐리 선택절차를 이용한 부호확장제거방법과 결합함으로서 새로운 곱셈기구현 방안을 제시한다. 이 곱셈기의 응용으로서 SSB/BPSK-DS/CDMA 전송방식에 사용되는 힐버트 트랜스포머를 43탭 FIR 필터로 구현하고 기존의 compensation 벡터 방법과 비교하여 약 34%의 부호확장 오버헤드를 줄일 수 있음을 보인다.

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Design of Montgomery Modular Multiplier based on Systolic Array (시스토릭 어레이를 이용한 Montgomery 모듈라 곱셈기 설계)

  • 하재철;문상재
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.9 no.1
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    • pp.135-146
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    • 1999
  • Most public key cryptosystems are constructed based on a modular exponentiation, which is further decomposed into a series of modular multiplications. We design a new systolic array multiplier to speed up modular multiplication using Montgomery algorithm. This multiplier with simple circuit for each processing element will save about 14% logic gates of hardware and 20% execution time compared with previous one.

Design of High Speed Modular Multiplication Using Hybrid Adder (Hybrid 가산기를 이용한 고속 모듈러 곱셈기의 설계)

  • Lee, Jae-Chul;Lim, Kwon-Mook;Kang, Min-Sup
    • Proceedings of the Korea Information Processing Society Conference
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    • 2000.10a
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    • pp.849-852
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    • 2000
  • 본 논문에서는 RSA 암호 시스템의 Montgomery 모듈러 곱셈 알고리듬을 개선한 고속 모듈러 곱셈 알고리듬을 제안하고, Hybrid 구조의 가산기를 사용한 고속 모듈러 곱셈 알고리듬의 설계에 관하여 기술한다. 기존 Montgomery 알고리듬에서는 부분합계산시 2번의 덧셈연산이 요구되지만 제안된 방법에서는 단지 1번의 덧셈 연산으로 부분 합을 계산할 수 있다. 또한 덧셈 연산 속도를 향상시키기 위하여 Hybrid 구조의 가산기를 제안한다. Hybrid 가산기는 기존의 CLA(Carry Look-ahad Adder)와 CSA(Carry Select Adder)알고리듬을 혼합한 구조를 기본으로 하고 있다. 제안된 고속 모듈러 곰셈기는 VHDL(VHSIC Hardware Description Language)을 이용하여 모델링하였고, $Synopsys^{TM}$사의 Design Analyzer를 이용하여 논리합성(Altera 10K lib. 이용)을 수행하였다. 성능 분석을 위하여 Altera MAX+ PLUS II 상에서 타이밍 시뮬레이션을 수행하였고, 실험을 통하여 제안한 방법의 효율성을 입증하였다.

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Design of MSB-First Digit-Serial Multiplier for Finite Fields GF(2″) (유한 필드 $GF(2^m)$상에서의 MSB 우선 디지트 시리얼 곱셈기 설계)

  • 김창훈;한상덕;홍춘표
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.6C
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    • pp.625-631
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    • 2002
  • This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.