• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.5
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• pp.11-22
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• 2010

Recently, Fan and Dai introduced a Shifted Polynomial Basis and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. As the name implies, the SPB is obtained by multiplying the polynomial basis 1, ${\alpha}$, ${\cdots}$, ${\alpha}^{n-1}$ by ${\alpha}^{-\upsilon}$. Therefore, it is easy to transform the elements PB and SPB representations. After, based on the Modified Shifted Polynomial Basis(MSPB), SPB bit-parallel Mastrovito type I and type II multipliers for all irreducible trinomials are presented. In this paper, we present a bit-parallel architecture to multiply in SPB. This multiplier have a space complexity efficient than all previously presented architecture when n ${\neq}$ 2k. The proposed multiplier has more efficient space complexity than the best-result when 1 ${\leq}$ k ${\leq}$ (n+1)/3. Also, when (n+2)/3 ${\leq}$ k < n/2 the proposed multiplier has more efficient space complexity than the best-result except for some cases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• Journal of the Korea Society of Computer and Information
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• v.28 no.2
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• pp.69-75
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• 2023

Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.3
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• pp.1-8
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• 2002

Modular Multiplication in Galois Field GF(2/sup m/) is a basic operation for many applications, particularly for public key cryptography. This paper presents a new architecture that can process modular multiplication on GF(2/sup m/) per m clock cycles using a cellular automata. Proposed architecture is more efficient in terms of the space and time than that of systolic array. Furthermore it can be efficiently used for the hardware design for exponentiation computation.

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.1
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• pp.43-48
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• 2004

This paper presents new architectures based on the linear feedback shia resister architecture over GF(2m). First we design a modular multiplier and a modular squarer, then propose an architecture by combing the multiplier and the squarer. All architectures use an irreducible AOP (All One Polynomial) as a modulus, which has the properties of all coefficients with '1'. The proposed architectures have lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponentiation architecture, which is the con operation in public-key cryptosystems.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.17-25
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• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Journal of IKEEE
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• v.11 no.2
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• pp.83-88
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• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.342-349
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• 2008

This paper presents a new digit-serial systolic multiplier over $CF(2^m)$ for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every ${\lceil}m/D{\rceil}$ clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.351-355
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• 2006

RSA 암호 시스템은 IC카드, 모바일 및 WPKI, 전자화폐, SET, SSL 시스템 등에 많이 사용된다. RSA는 모듈러 지수승 연산을 통하여 수행되며, Montgomery 곱셈기를 사용하는 것이 효율적이라고 알려져 있다. Montgomery 곱셈기에서 임계 경로 지연 시간(Critical Path Delay)은 세 피연산자의 덧셈에 의존하고 캐리 전파를 효율적으로 처리하는 문제는 Montgomery 곱셈기의 효율성에 큰 영향을 미친다. 최근 캐리 전파를 제거하는 방법으로 캐리 저장 덧셈기(Carry Save Adder, CSA)를 사용하는 연구가 계속 되고 있다. McIvor외 세 명은 지수승 연산에 최적인 CSA 3단계로 구성된 Montgomery 곱셈기와 CSA 2단계로 구성된 Montgomery 곱셈기를 제안했다. 시간 복잡도 측면에서 후자는 전자에 비해 효율적이다. 본 논문에서는 후자보다 빠른 연산을 수행하기 위해 캐리 전파 제거 특성을 가진 이진 부호 자리(Signed-Digit, SD) 수 체계를 사용한다. 두 이진 SD 수의 덧셈을 수행하는 잉여 이진 덧셈기(Redundant Binary Adder, RBA)를 새로 제안하고 Montgomery 곱셈기에 적용한다. 기존의 RBA에서 사용하는 이진 SD 덧셈 규칙 대신 새로운 덧셈 규칙을 제안하고 삼성 STD130 $0.18{\mu}m$ 1.8V 표준 셀 라이브러리에서 지원하는 게이트들을 사용하여 설계하고 시뮬레이션 하였다. 그 결과 McIvor의 2 방법과 기존의 RBA보다 최소 12.46%의 속도 향상을 보였다.