• Journal of Advanced Marine Engineering and Technology
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• v.31 no.5
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• pp.575-582
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• 2007

In this paper, a 100 Watt high power amplifier has been implemented and performed evaluation, which is operating at UHF band ($470\;{\sim}\;806\;MHz$) for Digital TV repeater. To achieve increase of bandwidth and high power capability, 3-way power combiner and divider of Wilkinson type was adopted. In order to measure the fabricated 100 Watt power amplifier, the estimation technique function which makes equivalent mask was used. As a result of the measurement, the existence of pilot signal is confirmed and the signal transmitted at the rated output power 100 Watt is brought out the flat feature through 6 MHz bandwidth. and it resulted that its value was less than -47 dB at the edge of radiation channel and less than -110 dB at more than 6 MHz position from channel edge.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1326-1331
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• 2001

This paper has been studied about design of a transceiver for data transmission. The transceiver has bandwidth of 424.7~424.95 MHz and uses half duplex communication method, PLL synthesized, 20 channel, 12.5 KHz channel bandwidth and FSK modulation/demodulation method. The transmission set is designed using low noise amplifier and power amplifier Also, it consists of low pass filter and resonation circuit for decrease of spurious signal. The receiver set is designed using dual conversion method. Finally, the transceiver set achieves the following characteristics 9.71dbm output power, 47dbc spurious property and $\pm$12.3 Jitter at sensitivity of -1134dbm.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.29-33
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• 2002

본 논문은 자기 바이어스(self bias)를 이용한 PCS 대역용 하이브리드 전력 저잡음 증폭기(power LNA) 모듈에 관한 것으로 GaAs p-HEMT 칩을 세라믹 기판에 실장하여 와이어 본딩과 주변 매칭을 통해 고주파 손실을 줄이고 온도 변화에 대한 안정성과 1.2㏈의 저잡음, 21~23㏈m의 P$_1$㏈를 실현하였다. 10mm$\times$10mm 크기로 표면 실장이 되도록 단자를 cut-line 형태로 모듈화 하여 안정성과 신뢰성을 향상시켰고 또한 저가격화를 실현하였다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.113-117
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• 2003

This paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard $0.25{\mu}m$ CMOS technology and is shown to deliver 100mW output power to load with 41% power added efficiency(PAE) from a 2.5V supply.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.509-509
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• 2012

RF는 사이클로트론에서 빔을 원하는 에너지로 가속하기 위해 쓰인다. MC50 사이클로트론에는 두 개의 DEE가 있고 각각 독립된 LLRF모듈과 증폭기를 통해 제어된다. 주요 제어변수는 DEE1,2의 Voltage와 양단간의 Phase인데 이는 RF Generator에서 특정 주파수로 발생된 RF 시그널의 Amplitude와 Phase를 RF Modulator에서 변조하므로 제어되어진다. 지금 현재의 Modulator는 오래되어 DEE Voltage의 컨트롤이 잘 이루어지지 않고 있고 가끔 연결부위에서 문제를 보여 새 Modulator를 제작하게 되었다. 새로 제작된 Modulator를 구형과 비교해 볼 때 Driving Amplifier에서 소모되는 전력이 7~14% 줄어드는 효과를 볼 수 있었다.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.335-339
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• 2003

This Paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard 0.25$\mu\textrm{m}$ CMOS technology and is shown to deliver 100mW output Power to load with 41％ power added efficiency(PAE) from a 2.5V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1532-1535
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• 2009

This paper describes a K-band CW radar transceiver suitable for power saving motion sensor. The presented transceiver module is designed and contains patch antennas, dielectric resonator oscillator (DRO), IF amplifier, mixer, divider. The designed divider and antenna are measured and the transmitting frequency and the power were fairly good for using in commercial applications. The transceiver is manufactured with a dimension of 35${\times}$35${\times}$10(mm) and can be adapted in various applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1083-1090
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• 2015

We designed and manufactured Ka-band SSPA include drive amplifier and high power amplifier MMICs by $0.15{\mu}m$ GaN commercial process. Also, we fabricated main components micro-strip line to WR28 waveguide transition and WR28 wave guide power combiner for Ka-band SSPA. This Ka-band SSPA shows saturated output power 44.2 dBm, power added efficiency 16.6 % and power gain 39.2 dB at 29~31 GHz frequency band.