• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.3
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• pp.126-131
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• 2014

In this study, QRS complex is detected by Wavelet Transform and it can be worked in 32bit fixed point operation thought optimization. First, ECG signal is passed though band pass filter. Second, it is transformed using one-band combined wavelet function from 3-band wavelet function. Third, it is passed though moving window integral. Finally, QRS complex is detected by decision rule. The proposed algorithm is evaluated using MIT-BIH arrhythmia database. Its all of process make progress 32-bit fixed-point operation and it makes table that high complexity operations like trigonometrical function. The detection algorithm evaluate through computer simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.80-83
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• 2010

This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.161-164
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• 2000

본 논문에서는 최근 휴대용 오디오 기기 등에서 활발하게 사용되고 있는 MP3 (MPEG-1,2 계충-III) 오디오 복호화 알고리듬을 실시간 구현하였다. 휴대용 기기에 적합한 저전력 설계를 위하여 16비트 고정 소수점 범용 DSP인 모토로라 DSP56654를 이용하였고, 연산량을 줄이기 위한 작업을 수행하였다. 또한 음질 열화를 최소화하고 CD 수준의 고음질을 얻기 위해서 각 복호화 과정에 대한 최적의 고정소수점 연산을 연구하였다. 구현된 복호화기는 약 40MIPS 정도의 연산량으로 90dB이상의 SNR을 갖는 최종 PCM 샘플을 생성한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.59-63
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• 1999

본 논문에서는 국제 표준화기구(ISO) 산하의 동영상 전문가 그룹(MPEG)의 오디오 압축방법들중 하나인 MPEG-I layer 3의 복호화기를 고정 소수점으로 변환한 후, OalkDSPCore$\circledR$를 기반으로 전 과정을 어셈블리어로 실시간 구현하였다. 실시간 구현에 사용된 OakDSPCor$\circledR$는 DSPGroup사에서 개발된 저전력 소비형 16-비트 고정소수점 DSPCore로서 40MIPS의 성능을 가지고 있으며, 음성/오디오, 통신, 디지털 셀룰라폰 같은 소비자의 맞게 ASIC화할 수 있는 장점을 가지고 있다. 구현된 MP3 복호화기는 약33 MIPS의 복잡도를 나타내며, 사용된 메모리양은 프로그램 ROM 3.1Kwords, 데이터 ROM(table)10.82Kwords 및 RAM6.1Kwords이다. 구현된 MP3 복호화기는 OMNI-MEDIASOUND에서 제공하는 4개의 test 벡터들을bit-exact하게 통과하였다.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.149-155
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• 2007

In this paper, we propose an real-time implementation of JPEG2000 codec on the ARM9 processor. The implemented codec is designed to separate control codes from data management codes in order to use effectively the system resources such as processor and memory. Especially, in embedded situations like cellular phones it is very important to provide good services using limited processor and internal memory. Since ARM9 series processors do not provide floating-point, large amount of computational time is required to perform the operation which needs highly repetitive floating-point computations like DWT(discrete wavelet transform). The proposed codec was programed using fixed-point to overcome this weakness. Also code optimization considering cache memory was applied to further improve the computational speed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.81-88
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• 2004

Turbo code has been adopted in the 3GPP standard, since its performance is very close to the Shannon limit. However, the turbo decoder requires a lot of computations and the amount of the memory increases as the block size of turbo codes becomes larger. In order to reduce the complexity of the turbo decoder, the Log-MAP, the Max-Log-MAP and the sliding window algorithm have been proposed. In this paper, the performance of turbo codes adopted in the 3GPP standard is analyzed by using the floating point and the fixed point implementation. The efficient decoding method is also proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.128-136
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• 2002

In this paper, we developed an acoustic echo canceller in real-time using TeakLite DSP Core, which will be placed in the vocoder chip of a mobile handset. Considering the limited computational capacity given to the acoustic echo canceller in a vocoder chip, we employed a FIR-type adaptive filter using a conventional NLMS algorithm. To begin with, we designed and implemented an acoustic echo canceller with floating-point format C-source code, and then converted it into fixed-point format through integer simulation. Then we programmed and optimized it in the assembler level to make it run ill real-time. After optimization procedure, the implemented echo canceller has approximately 624 words of program memory and 811 words of data memory. With 8 KHz sampling rate and 256 filter taps in the echo canceller that corresponds to 32 msec of echo delay, it requires 14.12 MIPS of computational capacity. For coverage of 16 msec echo delay, i.e., 128 filter taps, 9 MIPS is requited.