• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.820-822
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• 2005

We have designed a 32-bit microprocessor with fixed point digital signal processing functionality. This processor, combines both general-purpose microprocessor and digital signal processor functionality using the reduced instruction set computer design principles. It has functional units for arithmetic operation, digital signal processing and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline stucture.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.552-557
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• 2000

In the paper, we proposed a face recognition method that uses GA-BP(Genetic Algorithm-Back propagation Network) that optimizes initial parameters such as bias values or weights. Each pixel in the picture is used for input of the neuralnetwork. The initial weights of neural network is consist of fixed-point real values and converted to bit string on purpose of using the individuals that arte expressed in the Genetic Algorithm. For the fitness value, we defined the value that shows the lowest error of neural network, which is evaluated using newly defined adaptive re-learning operator and built the optimized and most advanced neural network. Then we made experiments on the face recognition. In comparison with learning convergence speed, the proposed algorithm shows faster convergence speed than solo executed back propagation algorithm and provides better performance, about 2.9% in proposed method than solo executed back propagation algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The KIPS Transactions:PartB
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• v.9B no.6
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• pp.715-726
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• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.50-58
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• 2013

In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion.

• Journal of Broadcast Engineering
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• v.25 no.4
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• pp.587-597
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• 2020

In this paper, we analyze the normalization that occurs when processing digital hologram and propose an optimized quantization method. In JPEG Pleno, which standardizes the compression of holograms, full complex holograms are defined as complex numbers with 32-bit or 64-bit precision, and the range of values varies greatly depending on the method of hologram generation and object type. Such data with high precision and wide dynamic range are converted to fixed-point or integer numbers with lower precision for signal processing and compression. In addition, in order to reconstruct the hologram to the SLM (spatial light modulator), it is approximated with a precision of a value that can be expressed by the pixels of the SLM. This process can be refereed as a normalization process using quantization. In this paper, we introduce a method for normalizing high precision and wide range hologram using quantization technique and propose an optimized method.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.52-57
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• 2005

The adaptive multirate wideband (AMR-WB) speech coder has an extended audio bandwidth from 50 Hz to 7 kBz and operates on nine speech coding bit-rates from 6.6 to 23.85 kbit/s. In this Paper, we present the real-time implementation of AMR-WB speech coder using 16bit fixed-point TMS320C5509 that has dual MAC units. Firstly, We implemented AMR-WB speech coder in C 1anguage level using intrinsics, and then performed optimization in assembly language. The computational complexity of the implemented AMR-WB coder at 23.85 kbit/s is 42.9 Mclocks. And this coder needs the program memory of 15.1 kwords, data ROM of 9.2 kwords and data RAM of 13.9 kwords.

• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.78-83
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• 2000

Vocoders used in digital mobile phone adopt new improved algorithm to achieve better communication quality. Therefore the communication problem occurs between mobile phones using different vocoder algorithms. In this paper, the efficient implementation of 8kbps and 13kbps QCELP into one DSP chip to solve this problem is presented. We also describe the optimization method at each level, that is, algorithm-level, equation-level, and coding-level, to reduce the complexity for the QCELP vocoder algorithm implementation. The complexity in the codebook search-loop that is the main part for the QCELP algorithm complexity can be reduced about 50% by using these optimizations. The QCELP implementation with our DSP requires only 25 MIPS of computation for the 8kbps and 33 MIPS for the 13kbps ones. The DSP for our real-time implementation is a 16-bit fixed-point one specifically designed for vocoder applications and has a simple architecture compared to general-purpose ones in order to reduce the power consumption.