• Title/Summary/Keyword: 고속 알고리듬

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Design and Implementation of High-Speed Pattern Matcher Using Multi-Entry Simultaneous Comparator in Network Intrusion Detection System (네트워크 침입 탐지 시스템에서 다중 엔트리 동시 비교기를 이용한 고속패턴 매칭기의 설계 및 구현)

  • Jeon, Myung-Jae;Hwang, Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.11
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    • pp.2169-2177
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    • 2015
  • This paper proposes a new pattern matching module to overcome the increased runtime of previous algorithm using RAM, which was designed to overcome cost limitation of hash-based algorithm using CAM (Content Addressable Memory). By adopting Merge FSM algorithm to reduce the number of state, the proposed module contains state block and entry block to use in RAM. In the proposed module, one input string is compared with multiple entry strings simultaneously using entry block. The effectiveness of the proposed pattern matching unit is verified by executing Snort 2.9 rule set. Experimental results show that the number of memory reads has decreased by 15.8%, throughput has increased by 47.1%, while memory usage has increased by 2.6%, when compared to previous methods.

Side-Channel Cryptanalysis on Stream Cipher HC-128 for Mobile Ad-Hoc Network Environments (이동 Ad-Hoc 네트워크 환경에 적합한 스트림 암호 HC-128의 부채널 안전성 분석)

  • Bae, KiSeok;Park, YoungHo;Moon, SangJae
    • Journal of Korea Society of Industrial Information Systems
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    • v.17 no.6
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    • pp.11-17
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    • 2012
  • The HC-128 stram cipher which selected for the final eSTREAM portfolio is suitable for mobile Ad-Hoc network environments because of the ability of high-speed encryption in restricted memory space. In this paper, we analyzed the vulnerability of side channel analysis attack on HC-128 stream cipher. At the first, we explain a flaw of previous theoretical analysis result which defined the complexity of side-channel attack of HC-128 stream cipher as 'low' and then re-evaluate the security against side-channel attack by estimating the concrete complexity for recovering the secret key. As a result, HC-128 stream cipher is relatively secure against side-channel attack since recovering the secret key have $2^{65}$ computation complexity which is higher than other stream cipher's one.

A High Performance Modular Multiplier for ECC (타원곡선 암호를 위한 고성능 모듈러 곱셈기)

  • Choe, Jun-Yeong;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.961-968
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    • 2020
  • This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.

A High-Performance ECC Processor Supporting NIST P-521 Elliptic Curve (NIST P-521 타원곡선을 지원하는 고성능 ECC 프로세서)

  • Yang, Hyeon-Jun;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.4
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    • pp.548-555
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    • 2022
  • This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

Selective Inter-layer Residual Prediction Coding and Fast Mode Decision for Spatial Enhancement Layers in Scalable Video Coding (스케일러블 비디오 부호화에서 선택적 계층간 차분 신호 부호화 및 공간적 향상 계층에서의 모드 결정)

  • Lee, Bum-Shik;Hahm, Sang-Jin;Park, Chang-Seob;Park, Keun-Soo;Kim, Mun-Churl
    • Journal of Broadcast Engineering
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    • v.12 no.6
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    • pp.596-610
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    • 2007
  • In order to reduce the complexity of SVC encoding, we introduce a fast mode decision method in the enhancement layers of spatial scalability by selectively performing the inter-layer residual prediction of SVC. The Inter-layer residual prediction coding in Scalable Video Coding has a large advantage of enhancing the coding efficiency since it utilizes the correlation between two residuals from a lower spatial layer and its next higher spatial layer. However, this entails the dramatical increase in the complexity of SVC encoders. The proposed method is to analyze the characteristics of integer transform coefficients for the subtracted signal for two residuals from lower and upper spatial layers. Then it selectively performs the inter-layer residual prediction coding and rate-distortion optimizations in the upper spatial enhancement layer if the SAD values of residuals exceed adaptive threshold values. Therefore, by classifying the residuals according to the properties of integer-transform coefficients only with SAD of residuals between two layers, the SVC encoder can perform the inter-layer residual coding selectively, thus significantly reducing the total required encoding time. The proposed method results in reduction of the total encoding time with 51.5% in average while maintaining the RD performance with negligible amounts of quality degradation.

Sparse Adaptive Equalizer for ATSC DTV in Fast Fading Channels (고속페이딩 채널 극복을 위한 ATSC DTV용 스파스 적응 등화기)

  • Heo No-Ik;Oh Hae-Sock;Han Dong Seog
    • Journal of Broadcast Engineering
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    • v.10 no.1 s.26
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    • pp.4-13
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    • 2005
  • An equalization algorithm is proposed to guarantee a stable performance in fast fading channels for digital television (DTV) systems from the advanced television system committee (ATSC) standard. In channels with high Doppler shifts, the conventional equalization algorithm shows severe performance degradation. Although the conventional equalizer compensates poor channel conditions to some degree, long filter taps required to overcome long delay profiles are not suitable for fast fading channels. The Proposed sparse equalization algorithm is robust to the multipaths with long delay Profiles as well as fast fading by utilizing channel estimation and equalizer initialization. It can compensate fast fading channels with high Doppler shifts using a filter tap selection technique as well as variable step-sizes. Under the ATSC test channels, the proposed algorithm is analyzed and compared with the conventional equalizer. Although the proposed algorithm uses small number of filter taps compared to the conventional equalizer, it is stable and has the advantages of fast convergence and channel tracking.

Statistical Characteristics and Complexity Analysis of HEVC Encoder Software (HEVC 부호화기 소프트웨어의 통계적 특성 및 복잡도 분석)

  • Ahn, Yongjo;Hwang, Taejin;Yoo, Sungeun;Han, Woo-Jin;Sim, Donggyu
    • Journal of Broadcast Engineering
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    • v.17 no.6
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    • pp.1091-1105
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    • 2012
  • In this paper, we analyzed statistical characteristics and complexity of HEVC encoder as a leading research of acceleration, optimization and parallelization. Computational complexity of the HEVC encoder is approximately twice the compression performance compared to H.264/AVC. But, the increase of encoder complexity remains a problem to be solved in the future. Before performing the research on acceleration, optimization and parallelization to reduce high complexity of HEVC encoder, we measure the complexity each module for HEVC encoder using it's reference software HM 7.1. We also measured the predicted complexity of fast HEVC encoder software, used in real applications, using HM 7.1 applying fast encoding method. The complexity is measured in terms of the operating cycle of the encoder software under the common test sequences and conditions in the Windows PC environment. In addition, we analyze statistical characteristics of HEVC encoder software according to encoding structures and limitation using coded bitstreams.

Performance Enhancement of Call Admission Control in an Adaptive Array Antenna System (적응형 어레이 안테나 시스템에서의 호 수락제어 알고리즘 성능 개선에 관한 연구)

  • Kim, Min-Jung;Kim, Nak-Myeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.9A
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    • pp.1013-1021
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    • 2004
  • In the WCDMA mobile multimedia communication system, the adaptive array antenna IS adopted to improve the performance of the system by reducing inter-user interference using antenna beam control. Usually, the interference resulted from the higher data rate users is much more significant to the lower data rate users than the other way around, so the overall performance can be enhanced by reducing the interference from higher data rate users. In order to maximize the efficiency of adaptive antenna operation, an optimal call admission control, especially during handoff, adaptive to the data rates is a critical problem. In this paper, We propose a call admission control algorithm based on the Soft QoS concept for the efficient processing of the handoff of higher data rate calls, and an adaptive handoff control mechanism according to the data rates. The proposed algorithm has been evaluated by computer simulation that it accommodates high data rate users among many lower data rate users much better, and the average call blocking probability for lower rate users becomes much lower than the conventional call admission control algorithm.

Image Compression Using DCT Map FSVQ and Single - side Distribution Huffman Tree (DCT 맵 FSVQ와 단방향 분포 허프만 트리를 이용한 영상 압축)

  • Cho, Seong-Hwan
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.10
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    • pp.2615-2628
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    • 1997
  • In this paper, a new codebook design algorithm is proposed. It uses a DCT map based on two-dimensional discrete cosine of transform (2D DCT) and finite state vector quantizer (FSVQ) when the vector quantizer is designed for image transmission. We make the map by dividing input image according to edge quantity, then by the map, the significant features of training image are extracted by using the 2D DCT. A master codebook of FSVQ is generated by partitioning the training set using binary tree based on tree-structure. The state codebook is constructed from the master codebook, and then the index of input image is searched at not master codebook but state codebook. And, because the coding of index is important part for high speed digital transmission, it converts fixed length codes to variable length codes in terms of entropy coding rule. The huffman coding assigns transmission codes to codes of codebook. This paper proposes single-side growing huffman tree to speed up huffman code generation process of huffman tree. Compared with the pairwise nearest neighbor (PNN) and classified VQ (CVQ) algorithm, about Einstein and Bridge image, the new algorithm shows better picture quality with 2.04 dB and 2.48 dB differences as to PNN, 1.75 dB and 0.99 dB differences as to CVQ respectively.

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Improved Differential Detection Scheme of Space-Time Trellis Coded MDPSK For MIMO (MIMO에서 시공간 부호화된 MDPSK의 성능을 향상시키기 위한 차동 검파 시스템)

  • Kim, Chong-Il;Lee, Ho-Jin;Yoo, Hang-Youal;Kim, Jin-Yong;Kim, Seung-Youal
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.10
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    • pp.1869-1876
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    • 2006
  • Recently, STC techniques have been considered to be candidate to support multimedia services in the next generation mobile radio communications and have been developed the many communications systems in order to achieve the high data rates. In this paper, we Nose the Trellis-Coded Differential Space Time Modulation system with multiple symbol detection. The Trellis-code performs the set partition with unitary group codes. The Viterbi decoder containing new branch metrics is introduced in order to improve the bit error rate (BER) in the differential detection of the unitary differential space time modulation. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency.