• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.820-828
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• 2008

In order to achieve high coding efficiency, H.264/AVC video coding standard adopts the techniques such as variable block size coding, motion estimation with quarter-pel precision, multiple reference frames, rate-distortion optimization, and etc. However, these coding methods have a defect to greatly increase the complexity for motion estimation. Particularly, from multiple reference frame motion estimation, the computational burden increases in proportion to the number of the searched reference frames. Therefore, we propose the method to reduce the complexity by controlling the number of the searched reference frames in motion estimation. Proposed algorithm uses the optimal reference frame information in both $P16{\times}16$ mode and the adjacent blocks, thus omits unnecessary searching process in the rest of inter modes. Experimental results show the proposed method can save an average of 57.31% of the coding time with negligible quality and bit-rate difference. This method also can be adopted with any of the existing motion estimation algorithm. Therefore, additional performance improvement can be obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Journal of Biomedical Engineering Research
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• v.19 no.2
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• pp.189-198
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• 1998

3D medical image reconstruction techniques are useful to figure out complex 3D structures from the set of 2D sections. In the paper, 3D medical image reconstruction system is constructed under PC environment and programmed based on modular programming by using Visual C++ 4.2. The whole procedures are composed of data preparation, gradient estimation, classification, shading, transformation and ray-casting & compositing. Three speed optimization techniques are used for accelerating 3D medical image reconstruction technique. One is to reduce the rays when cast rays to reconstruct 3D medical image, another is to reduce the voxels to be calculated and the other is to apply early ray termination. To implement 3D medical image reconstruction system based on PC, speed optimization techniques are experimented and applied.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.86-93
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• 1997

A Design & Simulation Tools of Surface Acoustic Wave(SAW) Filters for Mobile Communication Systems, which is based on Optimization of Impulse Samples with Object Function of Amplitude, Ripple and Group Delay Characteristics, is developed and is also evaluated by designning and simulating the SAW IF Filter for PCS. In Optimization Process, fast calculation algorithm of Object Function is proposed. With this Design Tools, Transversal SAW IF Filters can be easily designed under limited conditions of small chip size and package size. It may be also applicable to wide Band Pass Filters in future Communication Systems such as FPLMTS.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.237-241
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• 2011

Stable operation of an industry crane becomes more important as current industry facilities become larger and operate at higher speeds. This paper proposes implementing a system for monitoring moving objects within safety lines of an industry crane by camera. The cost of implementing such a system is low, since it requires only a webcam and notebook computer. The detection algorithm of moving objects uses the feature extraction method by image differential histograms. The proposed system is robust to variations in the weather and environment. The area of the inside safety lines is considered and shadow removal algorithm is used for good performance of the system. The system is valuable for practical applications in the industry.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1777-1784
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• 2000

In this paper we suggested the chirp stitching algorithm and transmitter/receiver channel to a spaceborne high resolution SAR which enables wideband signal generation and processing with minimum hardware requirement. The transmitter channel generates two sub-band signals and then generate a wideband signal using chirp stitching algorithm and the receiver channel divides a wideband signal into two sub-band signals in order to overcome the high speed data handling capability of this spaceborne systems. We generated and processed a 100 MHz wideband signal evaluated the performance and verified the feasibility of the application of this chirp stitching algorithm and transmitter/receiver channel to spaceborne high resoultion SAR.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.57-64
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• 2003

Recently, it has been shown that cryptographic devices such as smart cards are vulnerable to power attacks. In this paper, by mixing the randomization concept and the folding in half for secret scalar integer on ECCs, we propose an efficient and fast scalar multiplication algorithm to resist against simple power analysis(SPA) and differential power analysis(DPA) attacks. Our proposed algorithm as a countermeasure against SPA and DPA is estimated as a 33% speedup compared to the binary scalar multiplication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.715-722
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• 2010

This paper describes a hardware design of hash function processor which implements Korean Hash Algorithm Standard HAS-160. The HAS-160 processor compresses a message with arbitrary lengths into a hash code with a fixed length of 160-bit. To achieve high-speed operation with small-area, arithmetic operation for step-operation is implemented by using a hybrid structure of 5:3 and 3:2 carry-save adders and carry-select adder. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency. The designed HAS-160 processor is verified by FPGA implementation, and it has 17,600 gates on a layout area of about $1\;mm^2$ using a 0.35-${\mu}m$ CMOS cell library.