• Title/Summary/Keyword: 고속 신호 주파수

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Faults Current Discrimination of Power System Using Wavelet Transform (웨이블렛 변환을 이용한 전력시스템 고장전류의 판별)

  • Lee, Joon-Tark;Jeong, Jong-Won
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.3
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    • pp.75-81
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    • 2007
  • Recently the subject of "wavelet analysis" has be drawn by both mathematical and engineering application fields such as Signal Processing, Compression/Decomposition, Wavelet-Neural Network, Statistics and etc. Even though its similar to Fourier analysis, wavelet is a versatile tool with much mathematical content and great potential for applications. Especially, wavelet transform uses localizable various mother wavelet functions in time-frequency domain. Therefore, wavelet transform has good time-analysis ability for high frequency component, and has good frequency-analysis ability for low frequency component. Using the discriminative ability is more easy method than other conventional techniques. In this paper, Morlet wavelet transform was applied to discriminate the kind of line fault by acquired data from real power transformation network. The experimental result presented that Morlet wavelet transform is easier, and more useful method than the Fast Fourier Transform(FFT).

Design of a 7-bit 2GSPS Folding/Interpolation A/D Converter with a Self-Calibrated Vector Generator (자체보정 벡터 발생기를 이용한 7-bit 2GSPS A/D Converter의 설계)

  • Kim, Seung-Hun;Kim, Dae-Yun;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.4
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    • pp.14-23
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    • 2011
  • In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

Development of the passive tag RF-ID system at 2.45 GHz (2.45 GHz 수동형 태그 RF-ID 시스템 개발)

  • 나영수;김진섭;강용철;변상기;나극환
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.8
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    • pp.79-85
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    • 2004
  • In this paper, the RF-ID system for ubiquitous tagging applications has been designed, fabricated and analysed. The RF-ID System consists of passive RF-ID Tag and Reader. The passive RF-ID tag consists of rectifier using zero-bias schottky diode which converts RF power into DC power, ID chip, ASK modulator using bipolar transistor and slot loop antenna. We suggest an ASK undulation method using a bipolar transistor to compensate the disadvantage of the conventional PIN diode, which needs large current Also, the slot loop antenna with wider bandwidth than that of the conventional patch antenna is suggested The RF-ID reader consist of patch array antenna, Tx/Rx part and ASK demodulator. We have designed the RF-ID System using EM and circuit simulation tools. According to the measured results, The power level of modulation signal at 1 m from passive RF-ID Tag is -46.76 dBm and frequency of it is 57.2 KHz. The transmitting power of RF-ID reader was 500 mW

A Study on the Next Generation Dedicated Short Range Communication System using OFDM (OFDM 방식의 차세대 단거리전용 통신 시스템 성능 개선에 관한 연구)

  • Kim, Man-Ho;Kang, Heau-Jo
    • Journal of Advanced Navigation Technology
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    • v.10 no.4
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    • pp.394-399
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    • 2006
  • In this paper, we investigated performance for 5.8GHz dedicated short range communication system using OFDM which will be applied to Intelligent transportation system services. The maximum speed of a vehicle in DSRC channel is very fast as 180km/h, so a service time is very short to serve a various traffic information if hand-off is not occurred. Therefore higher bit rate is required to proved advanced and intelligent service to the drivers of various vehicle and the data transmission rate of the next generation DSRC system if being promoted over 10Mbps. The signals received in Clarke & Gans channel have been simulated using the computer simulator.

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컷오프 진단법을 이용한 고속 측정법

  • Na, Byeong-Geun;Yu, Gwang-Ho;Lee, Yun-Seong;Jang, Hong-Yeong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.201-201
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    • 2011
  • 컷오프 진단법은 프로브 형태로 제작된 마이크로 웨이브 진단법으로, 간단한 수식을 통해 전자밀도, 전자온도 등의 측정이 가능하며, 장치나 분석방법이 매우 간단한 장점을 지닌다. 또한, 측정에 약 1 mW 정도의 적은 파워를 사용하여 플라즈마 상태를 거의 변화시키지 않으며, 공정 플라즈마에서도 사용이 가능하다. 그러나 컷오프 진단법을 사용한 측정은 다른 종류의 프로브와 마찬가지로, 약 1초 정도의 긴 시간이 필요로 하는 단점이 있다. 따라서 기존의 컷오프 진단법은 펄스 플라즈마나 토카막과 같이 빠르게 변하는 플라즈마를 측정하기에는 무리가 있다. 본 발표에서는 컷오프 진단법을 새로운 방법으로 구현하여 더욱 빠르게 측정할 수 있는 방법을 소개하고자 한다. 컷오프 프로브는 방사 안테나, 측정 안테나와 네트워크 분석기로 구성되어 있다. 네트워크 분석기는 두 안테나 사이의 플라즈마 투과 스펙트럼을 만드는데 쓰이며, 주파수 스캔 방법을 사용하여 스펙트럼을 만든다. 컷오프 진단법의 측정시간은 주파수 스캔에 걸리는 시간에 의해 결정된다. 본 발표에서는 측정을 빠르게 하고자 전혀 새로운 방법을 도입하였다. 펄스 형태의 단일신호를 플라즈마 투과 특성을 살피는데 이용하면 측정을 매우 빠르게 할 수 있다. 그래서 펄스제조기와 오실로스코프를 이용하여 스펙트럼을 얻는데 사용하였다. 이론적으로는 이 방법을 통해 측정시간을 수 nano second 수준으로 줄일 수 있다. 실험적으로는 micro second 정도의 시간으로 측정을 할 수가 있었으며, 동일한 스펙트럼 및 측정결과를 얻을 수 있었다. 또한 이 방법을 펄스플라즈마에 적용할 경우 수십 nano second 수준의 시간분해능으로 측정을 할 수가 있었다. 이 방법을 응용하면 토카막 언저리와 같이 매우 빠르게 변하며 반복되지 않는 플라즈마의 측정도 가능할 것으로 예상된다.

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A Design on High Frequency CMOS VCO for UWB Applications (UWB 응용을 위한 고주파 CMOS VCO 설계 및 제작)

  • Park, Bong-Hyuk;Lee, Seung-Sik;Choi, Sang-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.2 s.117
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    • pp.213-218
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    • 2007
  • In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.

A Study on the Characteristics Analysis and Design of High Sensitivity Silicon Photodiode for Laser Detector (레이저 검출용 고감도 실리콘 포토다이오드 제조 및 특성 분석에 관한 연구)

  • Lee, Jun-Myung;Kang, Eun-Young;Park, Keon-Jun;Kim, Yong-Kab
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.5
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    • pp.555-560
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    • 2014
  • In order to improve spectrum sensitivity of photodiode for detection of the laser wavelength at 850 nm ~ 1000 nm of near-infrared band, this study has produced silicon-based photodiode whose area is $5000{\mu}m{\times}2000{\mu}m$, and the thickness is $280{\mu}m$. It was packed by the TO-5 type. The electrical properties of the dark currents have valued of approximately 0.1 nA for 5 V reverse bias, while the capacitance showed 32.5 pF at frequency range of 1 kHz and about 32.4 pF at the range of 200 kHz for 0 V. In addition, the rising time of output signal was as fast response as 20.92 ns for 10V. For the optical properties, the best spectrum sensitivity was 0.57 A/W for 890 nm, while it was relatively excellent value of 0.37 A/W for 1,000 nm. Over all, there were good spectrum sensitivity for this diode over the range of 870 ~ 920 nm.

Fast Inverse Transform Considering Multiplications (곱셈 연산을 고려한 고속 역변환 방법)

  • Hyeonju Song;Yung-Lyul Lee
    • Journal of Broadcast Engineering
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    • v.28 no.1
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    • pp.100-108
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    • 2023
  • In hybrid block-based video coding, transform coding converts spatial domain residual signals into frequency domain data and concentrates energy in a low frequency band to achieve a high compression efficiency in entropy coding. The state-of-the-art video coding standard, VVC(Versatile Video Coding), uses DCT-2(Discrete Cosine Transform type 2), DST-7(Discrete Sine Transform type 7), and DCT-8(Discrete Cosine Transform type 8) for primary transform. In this paper, considering that DCT-2, DST-7, and DCT-8 are all linear transformations, we propose an inverse transform that reduces the number of multiplications in the inverse transform by using the linearity of the linear transform. The proposed inverse transform method reduced encoding time and decoding time by an average 26%, 15% in AI and 4%, 10% in RA without the increase of bitrate compared to VTM-8.2.

A Study on Adaptive Sine Soft Clipping Method for PAPR Reduction in OFDM System (OFDM 시스템의 PAPR 감소를 위한 Adaptive Sine Soft Clipping 기법에 관한 연구)

  • Yoo, Sun-Yong;Kim, Wan-Tae;Jo, Sung-Jun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.340-343
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    • 2007
  • OFDM (Orthogonal Frequency Division Multiplexing) system is robust to frequency selective fading and narrowband interference in high-speed data communications. However, an OFDM signal consists of a number of independently modulated subcarriers, which can give a large PAPR (peak-to-Average Power Ratio) when added up coherently. In this paper, we propose a new PAPR reduction method using Adaptive Sine Soft Clipping (ASS Clipping) to solve the PAPR problem. The proposed method reduce the PAPR and out-of-band spectrum by cutting down high frequency components. From computer simulation results, we analyze the PSD (Power Spectral Density) and BER (Bit Error Rate) performance as well as PAPR reduction performance when the ASS Clipping method is applied to OFDM system.

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Investigation of Power Bus Decoupling by the Screw Connection of the PCB to Chassis (나사를 이용한 기구물과 인쇄회로기판 연결이 전원단 잡음 감소에 미치는 영향 분석)

  • 권덕규;이신영;이해영;이재욱;배승민
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.10
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    • pp.1040-1047
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    • 2002
  • In this paper, we investigated noise decoupling on the power bus by the screw connection, used to the mechanical join and grounding of the PCB ground to chassis. The screw connection penetrates the power bus and then it affects noise propagation on the power bus. To verify effect of the screw connection, we compare bare board with board having screws connection with 0.5 mm separation between power bus and chassis. From these results, we observed that the power bus noise was decreased about 5 dB at the frequency range from 0.1 GHz to 1 GHz. Also, we verified that a 4-layer PCB with signal trace had the better signal quality up to 600 MHz by the screw connection. Therefore, these results will be useful in designing to the high speed circuit and chassis.