• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.37-52
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• 2004

In this paper, Multistage Adaptive Partial PIC eliminating effectively the multiple access and multipath interference for DS-CDMA based W-CDMA uplink system is designed and its performance is evaluated with computer simulation. By adaptively controlling the slope of the soft limiter with received signals, the efficiency of the soft limiter can be maximized and the better performance is obtained by solving error floor problem using further precise generation of interference signal. As a result, The proposed Multistage Adaptive Partial PIC with simple optimizing method for time-variant channel showed optimum performance at fewer stages. Besides fewer stages, the interference cancellation at the output of the rake receiver considerably reduced system complexity. The Multistage Adaptive Partial PIC with precise generation and efficient cancellation of interference signal can solve error eoor problem, resulted from initial false detection and improve system performance of high data rate system.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.117-124
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• 2009

In this paper, we have developed communication modules for ubiquitous transportation sensor network (u-TSN). The developed module can be used for intelligent transportation services. The developed systems are based on IEEE 802.11a and IEEE 802.11g technologies for vehicle and infrastructure systems, respectively. We have found that the throughput for the developed systems is at maximum around 15 Mbps. It is reduced to 10 Mbps at a long distance and high speed condition. The performance is enough to support traffic control services in dense traffic condition.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1178-1185
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• 2009

In this paper, a wideband ultra-high speed & high purity discrete frequency synthesizer having minimum 2.5 MHz step size was proposed. To achieve fast and wideband operation, discrete frequencies were synthesized by mixing of 3 different pre-synthesized 16 frequencies made from fixed PLL and frequency dividers. Frequencies with discrete 2.5 MHz step were produced in 710~1,610 MHz. The measured hopping response time was 350 nsec average, output level was 21.5 dBm average with 2.65 dB flatness, spurious and harmonics level were suppressed below -60 dBc, and phase noise was -94 dBc/Hz@100 Hz. Also, a new measurement method for synthesizer response time was described.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.130-131
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• 2011

박막의 제조는 많은 연구의 가장 기초가 되는 시편을 만드는 과정으로 현대의 과학기술에서 매우 중요한 공정 중의 하나이다. 그러나 이러한 박막의 제조는 제조하는 사람의 숙련도나 장치에 의존하며 경우에 따라서는 원하는 특성의 박막을 제조하는 것이 매우 어려운 작업이 되기도 한다. 따라서 경험이 없는 연구자의 경우는 때때로 까다로움과 번거로움을 느끼게 되며, 안정된 공정을 찾기까지 많은 시간을 소비 하게 된다. 특히 부적절한 증발방법의 선정에 따른 실험 결과는 경제적인 손실을 초래할 뿐만 아니라 실험하는 사람을 좌절시키는 가장 큰 요인이 되어왔다. 진공증착에 의한 박막의 제조는 증발법과 스퍼터링, 이온플레이팅 등의 방법이 있으며 이중 증발을 이용한 박막의 제조에는 저항가열 증발, 전자빔 가열 증발, 유도가열 증발 등의 방법으로 구분하고 있다. 저항가열 증발원은 가격이 저렴하다는 장점은 있으나 증발원이 손쉽게 파손되거나 증발량이 일정하지 않아 박막의 정밀 제어가 어려울 뿐만 아니라 때에 따라서는 1 ${\mu}m$ 이상의 후막 형성에도 어려움이 있는 등 많은 제약이 있다. 따라서 적절한 증발원의 선정이 실험의 효율성을 좌우하는 경우가 많다. 적절한 증발원의 선정과 효율적인 실험을 위해 증발원 제조회사에서는 증발원의 선정과 증발 조건과 관련된 자료를 카탈로그 형태로 발행하고 있다. 그러나 그러한 자료만으로는 객관적인 정보를 얻기에 충분하지 못한 경우가 많으며, 어떤 경우에는 저자 등의 경험과 일치하지 않는 정보도 포함하고 있었다. 전자빔 증발원은 냉각이 되는 Crucible에 물질을 담고 고전압의 전자빔으로 물질을 가열시켜 증발시키는 증발원으로 1960년대 이후 박막 제조 실험에 이용되기 시작하였다. 전자빔은 고순도의 피막 제조가 가능하고 증발물질의 교체가 쉬우며 고속 증발이 가능함은 물론 다층막의 제조가 용이하고 증발물질의 제조비용이 저렴하다는 장점이 있다. 이러한 장점 때문에 1970년대 이후에는 전자빔을 이용한 박막제조가 폭 넓게 이루어졌고 이때를 즈음하여 전자빔을 이용한 물질의 증발 특성이 논문으로 발표되기도 하였다. 본 연구에서는 증발에 관한 저자들의 경험을 바탕으로 저항가열과 전자빔을 이용하여 증발실험을 진행한 물질계를 중심으로 각 물질의 증발특성과 가장 효율적인 Liner 등에 대해 기술하였다. 특히, 각종 물질의 증발 특성을 체계화함은 물론 효율적인 증발 방법을 객관적인 Data와 함께 제공하여 효과적인 박막 제조 실험에 도움이 되고자 하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.1-12
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• 2013

Information Security System is implemented in software, hardware and FPGA device. Implementation of S/W provides high flexibility about various information security algorithm, but it has very vulnerable aspect of speed, power, safety, and performing ASIC is really excellent aspect of speed and power but don't support various security platform because of feature's realization. To improve conflict of these problems, implementation of recent FPGA device is really performed. The goal of this thesis is to design and develop a FPGA hardware accelerator for information security system. It performs as AES, SHA-256 and ECC and is controlled by the Integrated Interface. Furthermore, since the proposed Security Information System can satisfy various requirements and some constraints, it can be applied to numerous information security applications from low-cost applications and high-speed communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.3
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• pp.291-297
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• 2014

Due to the rapid increase in demand for transportation of human and freight in modern railway systems, the CBTC system has been proposed, which is the solution for improvement of the line capacity that has been limited by the conventional track circuit based train control system. In the CBTC system, higher reliability of the communication system should be guaranteed for the safety of passengers and trains. However, due to the inherent characteristics of the wireless channel environment, performance degradations are inevitable. The diversity techniques can increase the reliability of data transmission using multiple antennas. In this paper, we investigate the performance of the STBC in the railway channel environment. Rician fading model is used for the viaduct scenarios which take important roles in the railway system. Also, considered is the Doppler effect which is an important factor in the mobile communication system. Simulations are performed to analyze the performance of the STBC in various channel environments. Results show that the performance degradation due to the phase error in viaduct scenarios is independent of the diversity order but is affected by the constellation of the modulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2637-2642
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• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.9-10
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• 2016

최근 급속한 산업 발달로 인하여 기존의 수 MW급 대용량 인버터가 산업용 팬, 컴프레서, 고속 철도 시스템 등 여러 분야에 사용되면서 이와 관련된 대용량 인버터 연구가 활발히 진행 중이다. 이런 대용량 인버터는 고효율과 직병렬의 구성된 전력용반도체 소자를 동시다발적으로 제어되어야하기 때문에 멀티레벨 인버터의 구조가 가장 적합하다. Cascaded H-bridge 멀티레벨 인버터는 커패시터와 다이오드를 사용하지 않고 스위치만으로 구성하며, 필터를 따로 구성하지 않아도 정현파와 유사하게 전압을 출력할 수 있다. 이로 인해 고주파 감소 및 각 셀을 직렬로 연결하여 입력전압보다 높은 출력전압을 얻을 수 있다. 또한, 스위칭 방법에 따라 동일한 Cascaded H-bridge 멀티레벨인버터 토폴로지에서도 각 THD와 온도에 따른 손실이 달라질 수 있다. Cascaded H-bridge 멀티레벨 인버터에서 이용하는 스위칭 방식은 첫 번째로 유니폴라 방식을 기본으로 한 Phase-shift가 있다. 이는 180도 위상차를 갖는 2개의 레퍼런스 파형과 위상천이가 된 캐리어 파형의 비교로 PWM (Pulse Width Modulation) 을 수행한다. 두 번째 방식으로는 Level-shift가 있다. 이는 캐리어 파형을 IPD (In-Phase Disposition) 방식으로 수직적으로 대역폭이 연속적이게 나열하여 레퍼런스 파형과 비교하는 PWM방식이다. 본 논문에서는 Phase-shift와 Level-shift 방식에 따른 Cascaded H-bridge 인버터와 NPC (Neutral Point Clamped) 인버터를 결합한 토폴로지에서의 온도에 따른 손실을 분석하고, 시뮬레이션을 통하여 비교 분석하였다.