• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.7-14
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• 2008

In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.4
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• pp.108-116
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• 2002

This paper presents the measurements and evaluation of voltage waveforms due to human electrostatic discharge(ESD). The principle of operation and design rule of a new device for measuring the ESD fast transient voltages with very fast rise time were described. Peak values and rise time of ESD voltages derived from a charged human body under a variety of experimental conditions were examined. The frequency bandwidth of the proposed voltage measuring system ranges from DC to 400[㎒]. The ESD voltage waveform is nearly equal to the ESD current waveform and the peak amplitude of ESD current waveform is roughly proportional to the ESD voltage in each experimental conditions. A rapid approach results in a discharge voltage with a faster initial rise time than for a slow approach. The voltages caused by direct finger ESDs have an initial slope with a relatively long, 10∼30[ns] rise time, but the amplitude is small. On the other hand, the voltages caused by direct hand/metal ESDs have a steep initial s1ope with 1 ∼3[ns] rise time, but an initial spike is very big. As a consequence, it was found that the ESD voltage and current waveforms strongly depend on the approach speed and material of intruder. These measurement results would be useful to design the ESD protective devices.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.256-260
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• 2008

This paper describes an improvement of mount-time delay in NAND Flash file systems. To improve file system mount performance, this work configures a hierarchical storage system with byte-addressable NVRAM and NAND Flash memory, and let the meta data of a file system allocated in the NVRAM. Since the meta data are stored in NVRAM supporting data integrity some of the items, which are stored in Spare area and Object Header area of NAND Flash memory to control meta data of NAND Flash file system, could be eliminated. And also, this work eliminates the scanning operation of the Object Header area of previous work FRASH1.0. The scanning operation is definitely required to find out the empty Object Header address for storing the Object Header data and provokes a certain amount of performance loss in file generation and deletion. In this work, an implemented file system, so-called FRASH1.5, is demonstrated, featuring new data structures and new algorithms. The mount time of FRASH1.5 becomes twice as fast as that of the FRASH1.0. The performance in file generation gets improved by about $3{\sim}8%$. In particular, for most large-size files, the FRASH1.5 has 8 times faster mount time than YAFFS, without any performance loss as seen in the file generation.

• Journal of Internet Computing and Services
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• v.12 no.5
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• pp.21-28
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• 2011

Recently medical and entertainment applications using conducting textile are suggested, but the data of conducting threads are not characterized, classified and verified. Only the data sheet published by manufacturing companies is available. Thus we need to verify the performances of the threading threads in communication. And we need a guideline if the existing communication protocols can be used for the conducting threads communication or the new specific communication protocols have to be developed for the communication. This paper classifies the characteristics of conducting threads made by domestic and overseas companies. Based on the criteria we classified conducting threads into three classes: class A, class B and class C. Further we carried out experiments to verify the adaptability of existing simple serial communication protocols such as RS232. Six different conducting threads are used in experiments and the length of each thread was 0.5m, 1m, 2m and 3m. The data transmission rate and error rate are collected and analyzed. RS485 is very prone to error due to static electricity from human and environment. So it may not be appropriate as long-distance communication protocol up to 12km which is possible in theory. RS232 shows stable and error-less data transmission ability even though every conducting thread didn’t show transmission capability over RS232. USB protocol shows high data rate transmission but the distance cannot be exceeded over 2m. Additionally, USB requires stable power supply. But if the power is supplied through conducting thread, its function is not.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.9
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• pp.822-829
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• 2015

In this paper, the piezoelectric-hydraulic pump with a piezostack actuator as a driving source has been designed, fabricated, and evaluated for its application to UAV's brake system. The performance requirements of the piezoelectric-hydraulic pump were decided based on the requirements analysis of the target aircraft brake system. The geometric design of the piezoelectric-hydraulic pump to meet the performance requirements of the pump was conducted, and all components of the pump including the spring sheet type check valves were machined with close tolerance. By constructing a test apparatus for the performance check of the piezoelectric-hydraulic pump, the performance characteristics of the pump, such as the outlet flow rate for load-free condition and the outlet oil pressure for closed loop condition, have been evaluated. It has been found by the performance test result that the developed piezoelectric-hydraulic pump satisfies the design requirements effectively.