• Title/Summary/Keyword: 고속동작

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A Design of Authentication/Security Processor IP for Wireless USB (무선 USB 인증/보안용 프로세서 IP 설계)

  • Yang, Hyun-Chang;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.11
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    • pp.2031-2038
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    • 2008
  • A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

Intra-Body Communication System for Bio Sensors (생체센서를 위한 인체통신시스템)

  • Jung, Jae-Wook;Kang, Jung-Mo;Kim, Myung-Sik;Oh, Woo-Jin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.9
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    • pp.1749-1754
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    • 2007
  • In this paper, we propose a new Intra-body communication system for bio-sensor which is one of applications in PAN(Personal Area Network) using body channel. The communication systems for bio-sensor network usually transmits a lot of data acquired in sensor to the receiver in wrist or waist. So we deign the intra-body modem with high data rate, low power, and small size which are achieved by baseband communication techniques. It is noted that the baseband transmission does not requires any analog IF and RF frontends, and can be operated in lower frequency than bandpass transmission. The proposed modem operates at 10MHz band according to the characteristics of intra-body channel, and shows the capability of 5Mbps data rate at distance of 20cm, with $BER=10^{-5}$. In addition, we implement the modem within $2{\times}2cm$ area.

Design Study for Power Integrity in Mobile Devices (모바일 기기의 전원 무결성을 위한 설계 연구)

  • Sa, Gi-Dong;Lim, Yeong-Seog
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.5
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    • pp.927-934
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    • 2019
  • Recently, mobile devices have evolved into small computers with various functions according to user requirements. Careful attention must be paid to the design of the power supply network for the stable operation of the application processor (AP), the wireless communication modem, the high performance camera, and the various interfaces of the mobile device to implement various functions of the mobile device. In this paper, we analyzed and verified the method of optimizing the design parameters such as the position, capacity, and number of decoupling capacitors to meet the target impedance required by the driver IC chip to ensure the stability of the power supply network of mobile devices that should be designed as wiring type due to mounting density limitation. The proposed wired power supply network design method can be applied to various applications including high-speed signal transmission line in addition to mobile applications.

Efficient Arc Detection and Control Method in Electro-discharge Machining (방전가공기의 효율적인 아크 검출과 제어방법)

  • Park, Yang-Jae
    • Journal of Digital Convergence
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    • v.16 no.12
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    • pp.309-315
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    • 2018
  • In this paper, propose an efficient arc detection and control method to achieve fast machining speed, improved precision and surface roughness in discharge machining, especially for carbide and hard material processing and metal processing using discharge phenomenon as energy. A single discharge waveform is divided into three sections of Td (Time-Delay), Ton (Time-on) and Toff (Time-off) and the gate control timing is simulated using the HDL language. In this paper, we analyze the effect of the gap between the electrode and the workpiece on the machining results by determining the operation of the servo mechanism by sampling the Td section through the comparator circuit. As a result of the analysis, the Td section of the formed waveform was more precisely sampled at a high speed and the results were improved when applied to the gap control between the electrode and the workpiece.

Processing Speed Improvement of Software for Automatic Corner Radius Analysis of Laminate Composite using CUDA (CUDA를 이용한 적층 복합재 구조물 코너 부의 자동 구조 해석 소프트웨어의 처리 속도 향상)

  • Hyeon, Ju-Ha;Kang, Moon-Hyae;Moon, Yong-Ho;Ha, Seok-Wun
    • Journal of Convergence for Information Technology
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    • v.9 no.7
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    • pp.33-40
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    • 2019
  • As aerospace industry has been activated recently, it is required to commercialize composite analysis software. Until now, commercial software has been mainly used for analyzing composites, but it has been difficult to use due to high price and limited functions. In order to solve this problem, automatic analysis software for both in-plane and corner radius strength, which are all made on-line and generalized, has recently been developed. However, these have the disadvantage that they can not be analyzed simultaneously with multiple failure criteria. In this paper, we propose a method to greatly improve the processing speed while simultaneously handling the analysis of multiple failure criteria using a parallel processing platform that only works with a GPU equipped with a CUDA core. We have obtained satisfactory results when the analysis speed is experimented on the vast structure data.

A Study on the Hardware Design of High-Throughput HEVC CABAC Binary Arithmetic Encoder (높은 처리량을 갖는 HEVC CABAC 이진 산술 부호화기의 하드웨어 설계에 관한 연구)

  • Jo, Hyun-gu;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.401-404
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    • 2016
  • This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

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Ground Ejection Tests to verify the Safe Separation of an Aircraft Mounted Store (항공기 장착 무장의 투하 안정성 검증을 위한 지상무장분리시험)

  • Lee, Jong-Hong;Choi, Seok-Min;Lee, Min-Hyoung;Lee, Chul;Jung, Jae-Won
    • Journal of Advanced Navigation Technology
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    • v.22 no.2
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    • pp.70-75
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    • 2018
  • The mounted store on an aircraft shall be subjected to an ground separation test to verify that a safe separation has been made before it is actually installed to the aircraft. In this study, ground ejection test was conducted with dummy missile to verify the stability of the drop on the land. Bomb rack unit essential to testing ground ejection test, operate at high pressure and produce a significant ejection force to push the missile away from any large orifice. Bomb rack unit modified their bombe pressure and orifice diameter to photograph the drop movement of dummy missile with high-speed camera and to analyze their drop displacement and speed. It is considered useful to provide the initial data for the ejection force analysis on aircraft with actual flight and to carry out the ground separation tests of aircraft with future developments.

Parallelized Architecture of Serial Finite Field Multipliers for Fast Computation (유한체 상에서 고속 연산을 위한 직렬 곱셈기의 병렬화 구조)

  • Cho, Yong-Suk
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.17 no.1
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    • pp.33-39
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    • 2007
  • Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

High-Speed Implementation to CHAM-64/128 Counter Mode with Round Key Pre-Load Technique (라운드 키 선행 로드를 통한 CHAM-64/128 카운터 모드 고속 구현)

  • Kwon, Hyeok-dong;Jang, Kyoung-bae;Park, Jae-hoon;Seo, Hwa-jeong
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.30 no.6
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    • pp.1217-1223
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    • 2020
  • The Block cipher CHAM is lightweight block cipher for low-end processors, developed by National Security Research Institute from Korea. The mode of operation is necessity for efficient operation of block cipher, among them, the counter (CTR) mode has good efficiency because it is easy to implement and supporting parallel operation. In this paper, we propose the optimized implementation for block cipher CHAM-CTR. The proposed implementation can be skipped some rounds by pre-computation. Thus it has better calculating speed than existing CHAM. Also, this implementation pre-load some of round keys to registers, before entering round functions. It makes reduced 160cycles loading time for round key load. Finally, proposed implementation achieved higher performance about 6.8%, and 4.5% for fixed-key scenario, and variable-key scenario, respectively.

Design of BLDC Motor Control Circuit for Electric Driver using UC3625 Controller IC (UC3625 Controller IC를 이용한 전동 Driver용 BLDC 전동기 제어회로 설계)

  • Jeong, Sungin
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.4
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    • pp.129-134
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    • 2021
  • A power tool is a tool used to manufacture and process various structures using a motor that is a power source. Using a motor that uses electricity as a power source, a reduction device, power transmission and conversion device functions are built-in to make the tool rotate, reciprocate, and vibrate. It is a work tool designed to assist the user's movement skills. In the case of Korea, the power tool industry has a short history and is lagging behind advanced countries such as Germany, the United States, and Japan in terms of technology level, market share, and recognition. In addition, electric drivers used in Korea are foreign products from the US and European countries, and the domestic market also prefers 100% foreign companies, and multinational companies are investing a lot in the domestic market. Therefore, technological development must follow in order to develop domestic technology and secure a consistently high market share. The purpose of this thesis is to design a motor driver with high output performance of motor performance, miniaturization, and high speed in accordance with the basic performance requirements of power tools, and finally research developments that can be applied to industrial and medical applications.