• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.1
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• pp.13-21
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• 2001

The discharge characteristics of 3 electrcdes AC surface discharge plasma display were analyzed. For an unstable state of the discharge which appeared at the maximum discharge voltage, it is found that a parbal erase of the wall charge by the second discharge is a cause. Based on the second discharge, new operation margin considering the interrelation between the address discharge and the display discharge was defined and the validity of it was verified by the experiments. It is necessary to decrease the acklress pulse width for high-speed addressing. However, the operation margin of the ackIress pulse decreases as the pulse width of it becomes narrower. If the address pulse width is wider than l[ps], the operation margin of the display discharge is not related to the address pulse width. From the experimental result, image or 8bit 253 gray level was displayed on PDP with the cell structure of the HDTV class by using the high-speed address ADS drive methcd with pulse width of $1[{\mu}s]$ and the brightness of $560[cd/m^2]$ was obtained. ained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1635-1641
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• 2021

Portable systems with built-in active noise control is required low power operation. Excessive anti noise search operation can lead to rapid battery consumption. A method that can adaptively cancel noise according to the operating conditions of the system is required and the methods of reducing power are becoming very important key feature in today's portable systems. In this paper, we propose the method of active noise control(ANC) using binary search algorithm in noisy systems. The implemented architecture detects a frequency component considered as noise from the input signal and by using the binary search algorithm, the system find out an appropriate amplitude value for anti-noise in a much faster time than the general linear search algorithm. Through the experimental results, it was confirmed that the proposed algorithm performs a successful functional operation.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.417-420
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• 2010

최근 UWB, IEEE802.11n과 같은 고속 무선 통신에서는 고속의 암호/복호 처리가 요구되고 있다. 본 논문은 UWB, Zigbee, IEEE802.11과 같은 최신 무선 통신 기술에서 보안 기능의 근간이 되는 CCM(CTR+CBC-MAC) 보안 모드 구현에 관한 것이다. AES와 같은 블록암호알고리즘과 결합된 CCM 기능을 하드웨어로 구현하는 방법을 제시한다. 특히, MAC, DMA모듈과 Hard-wired된 형태로 구현하여 통신속도 저하없이 무선 데이터 송/수신과 동시에 실시간으로 암호/복호 연산을 수행할 수 있으며, CCM 구동 clock을 최소화하여 고속 동작과 저전력 설계의 목적을 달성할 수 있다.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.366-369
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• 2003

현재 우리가 사용하고 있는 대부분의 시스템들은 대용량의 데이터를 송수신하고 있다. 대용량의 데이터를 전송하는 방법에는 여러방법이 있으나 한정되어 있는 대역폭을 사용하여 전송하기 위한 방법으로는 고속 전송을 사용한다. 많은 양의 데이터를 고속으로 전송을 하다 보면 여러가기 원인으로 인해 발생하는 지연에 대한 보정이 어려워 지게 된다. 이런 문제를 해결할 수 있는 방법중에 한가지가 바로 FDE(Fractional Delay Element)이다. FDE 는 1Clock 이하의 지연을 주는 소자로써 클럭 단위의 보정의 문제점을 해결한 것이다. 시스템 클럭을 고속으로 동작시키기에는 소자의 문제점이 있으나 FDE를 사용하면 시스템 클럭을 변화 없이 지연 보정을 할 수 있다. 본 논문에서는 VHDL 코딩과 FPGA 를 사용하여 FDE 를 구현 하였다. FDE 의 중요한 역할을 하는 FDF(Fractional Delay Filter)를 VHDL로 코딩을 하였다.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.3
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• pp.33-42
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• 2002

응용분야가 다양하고 고속 전송 및 노이즈 레벨의 주파수 대역에서 통신을 할 수 있는 UWB(Ultra Wide Band) 기술에 대한 관심이 증폭되고 있다. 울트라 쇼트 펄스파(ultra short pulse)에 정보를 실려 송수신하는 UWB 기술을 근거리 고속 통신이나 휴대용 단말기에 응용하고 저가격의 제품제작을 위하여 저전력 IC 개발은 핵심요소이다. 본 글에서는 UWB IC의 회로 구성 및 동작과 IC 개발업체의 현황을 논한다.