• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.56-65
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• 2006

The Quantum-dot Cellular Automata (QCA) can be considered as a candidate for the next generation digital logic implementation technology due to their small feature sizes and ultra low power consumption. Up to now, several designs using Uh technology have been proposed. However, we found not all of the designs function properly. Furthermore, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper, we show several critical vulnerabilities related to unbalanced input paths to QCA gates and sneak noise paths in QCA interconnect structures. In order to make up the vulnerabilities, a disciplinary guideline will be proposed. Also, we present a fast adder which has been designed by the discipline, and verified to be functional by the simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.98-105
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• 2008

FlexRay is a high-speed communications protocol with high flexibility and reliability. It was devised by automotive manufacturers and semiconductor vendors and implemented as on vehicle LAN protocol using x-by-wire systems. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, we first design the FlexRay communication controller, bus guardian protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay system was synthesized using Samsung $0.35{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 76 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with automobile advance alarm system in vehicle applications. The FlexRay system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of IKEEE
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• v.17 no.1
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• pp.36-43
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• 2013

This paper proposes a motion estimation algorithm with run-time adaptive workload control. It has optimized performance within limited hardware resources while guaranteeing hard realtime operation. It performs maximum searches within hard realtime constraints, since it determines search steps and workload adaptively. It reduces the hardware size to 1/4~1/400 of conventional algorithms, while its PSNR degradation is only 0.02~0.44 dB. It can be easily applied to most conventional fast algorithms, so it is useful to design realtime encoder chips.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.306.1-306.1
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• 2014

정보화 시대의 발전에 따라 점점 더 많은 정보를 더욱 빠르게 처리할 수 있는 기기들이 요구되고 있다. 메모리는 그 중에서 핵심적인 부품으로써 소자의 고집적화와 고속화가 계속 진행되면서 기존의 메모리 소자들은 집적화에서 그 한계에 도달하고 있다. 기존 소자들의 집적화의 한계를 극복하기 위하여 새로운 비휘발성 메모리 소자들이 제안되었다. 그 중 resistive switching random access memory(ReRAM)은 저항의 변화특성을 사용하는 메모리로 간단한 구조를 가지고 있기 때문에 집적화에 유리하다는 장점을 가지고 있다. 그 외에도 빠른 동작 속도와 낮은 전압에서의 동작이 가능하여 차세대 메모리로써 각광받고 있는 추세이다. 본 연구실에서는 이미 nitride 물질을 기반으로 한 여러 ReRAM 소자들을 제안해 왔다. 그 중 AlN-based ReRAM 소자는 빠른 동작 속도와 좋은 내구성을 보인 바 있다. 하지만 상업화를 위해서 해결해야 할 문제점들이 아직 존재하고 있다. 대표적으로 소자의 배열에서 각 소자의 균일한 동작이 보증되어야 하기 때문에 소자의 셋/리셋 전압의 산포를 줄이고 동작 전류 레벨을 낮추어야 할 필요성이 존재한다. 이러한 ReRAM의 이슈를 해결하기 위해, 본 실험에서는 기존의 AlN-based ReRAM 소자에 Ti를 도핑 방법을 이용하여 소자의 동작 전압 및 전류의 산포를 줄이기 위한 연구를 진행 하였다. 본 실험은 co-sputtering 방법을 이용하여 Ti가 도핑된 AlN을 저항변화 물질로 사용하여 그 특성을 살펴보았다. Ti의 도핑 효과로 소자의 신뢰성 향상 및 동작 전압의 감소 등의 효과를 얻을 수 있었다. 이는 nitride 기반 물질에서 Ti dopant에 의해 형성된 TiN의 효과로 설명된다. TiN는 metallic한 특성을 지니고 있기에 저항변화물질 내에서 일종의 metallic particle의 역할을 수행할 수 있다. 따라서 conducting path의 형성과정에서 이러한 particle 들이 전계를 유도하여 좀 더 균일한 set/reset 특성을 나타내게 된다.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.179-186
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• 2007

KTX control systems mutually control OBCS, ATC, MBU, TECA, MDT, ABU, HVAC, TRAE, PID and FDTR, KTX OBCS as master, and controls other sub-control devices as slave, using various serial lines. In order to analyze physical structure of various serial link lines and mutual data transmission structure, serial line analyzer is used in many ways. To use serial line analyzer, prior and professional technics about High Speed Train and experience of using device are necessary. In spite of difficult situation of space and environment where we work for maintenance of High Speed Train, in presenting basic structure about physical connection method aquired by sub-device serial line data collection and about communication data analysis, I hope that this research will be helpful for the person who work for similar area. Also, I hope that this research will help diagnostic work of High Speed Train, which is necessary for test run of independently developed High Speed Train.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.578-585
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• 2018

This paper proposes a design method for a 3-phase interior permanent magnet synchronous motor (IPMSM) and clamping force control method for an electro-mechanical brake (EMB) using co-simulation for a high-speed train (HST). A traditional pneumatic brake system needs much space for the compressor, brake reservoir, and air pipe. However, an EMB system uses up to 50% less space due to the use of a motor and electric wires for controlling the brake caliper. In addition, it can reduce the latency time for brake control because of the fast response and precise control. A train that has many brakes is advantageous for safety because of the control by sharing the braking force. In this paper, a driving method for a cam-shaft-type EMB is modeled. It is different from the ball-screw-type brakes that are widely used in automobiles. In addition, a co-simulation method is proposed using JMAG and Matlab/Simulink. The IPMSM was designed and analyzed with the JMAG tool, and the control system was simulated using Matlab/Simulink. The effectiveness of the co-simulation results of the mechanical clamping force and braking force was verified by comparison with the clamping force specifications of a HEMU-430X HST.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.65-77
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• 2009

This paper proposes fast image processing algorithms using SSE (Streaming SIMD Extensions) instructions. The CPU's supporting SSE instructions have 128bit XMM registers; data included in these registers are processed at the same time with the SIMD (Single Instruction Multiple Data) mode. This paper develops new SIMD image processing algorithms for Mean filter, Sobel horizontal edge detector, and Morphological erosion operation which are most widely used in automated optical inspection systems and compares their processing times. In order to objectively evaluate the processing time, the developed algorithms are compared with OpenCV 1.0 operated in SISD (Single Instruction Single Data) mode, Intel's IPP 5.2 and MIL 8.0 which are fast image processing libraries supporting SIMD mode. The experimental result shows that the proposed algorithms on average are 8 times faster than the SISD mode image processing library and 1.4 times faster than the SIMD fast image processing libraries. The proposed algorithms demonstrate their applicability to practical image processing systems at high speed without commercial image processing libraries or additional hardwares.