• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.987-992
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• 2002

In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2702-2704
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• 2003

본 논문은 전력선통신시스템 (Power Line Communications)을 위한 초고속 오류정정 부호화기 회로에 관한 설계방법론과 회로의 동작속도, 회로복잡성과 레이턴시에 직접적으로 기여하는 핵심 GF (Galois Field) 연산기들의 역할 및 이들의 설계결과에 관해 설명한다. 특히, 이러한 설계방법에 충실한 오류정정 부호화기회로는 입출력 병렬구조의 세미-시스톨릭 (Semi-systolic) 아키텍처를 갖는 고속의 내부 핵심 GF 연산기회로들을 채택함으로써 고속 연산을 가능토록 한다. 최적화된 GF곱셈연산기를 기반으로 설계되어진 리드-솔로몬 (Reed-Solomon) 오류정정 부호화기는 전력선 채널상에서 데이터를 전송 시 발생되는 연집오류들을 효과적으로 복원하도록 하는 대표적인 부호화기로 이미 존재하는 다른 회로들에 비해 동작속도, 회로의 복잡성, 및 레이턴시 측면에서 그 성능이 월등히 뛰어나므로, 실제 초고속 전력선 통신시스템의 설계 및 구현 시 효과적으로 이용될 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2000-2011
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• 2001

In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.168-172
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• 2009

Recently, while 3D sports game increases, the research that it recognizes the operation of the real user actively progresses. Most of all, the research about the golf is active. In this paper, the image acquiring in a high-speed CCD camera measures the flight data of the golf ball through the image processing. While photographing, the high-speed camera, using this system, exposes an image at regular intervals. And line scan camera checks whether the golf ball passed or not. After the location information of the calculated golf ball calculates a speed and a direction by using the physical formula, it applies the golf simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.9-15
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• 2009

In this paper, we invented a new structure of fast ATC(Automatic Threshold Control) circuit. Using the structure we made a new burst-mode limiting amplifier with fast ATC function using commercial $0.8{\mu}m$ BiCMOS technology. It's ATC function worked so fast that even the first bit of burst-data could be detected, which confirmed that the new structure was useful for fast ATC. However, in the beginning of a burst, distortions in duty-cycle occurred and increased up to 59% of duty-cycle as amplitude of input signal increased. But we confirmed that after 10 cycles passed, duty-cycles was staying below 52% of duty-cycle for any magnitude of input signal.

• Journal of the Korea Society of Computer and Information
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• v.5 no.4
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• pp.62-68
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• 2000

It was designed a high-speed analog input card that is a important device of ultrasonic testing flaw detector in the middle of non-destructive testing in this Paper. The A/D Board is inquired high-speed sampling rate and fast data acquisition system. This pater shows a design that has a function of Peak- Detection for ultrasonic testing by ISA Bus type and a 50MHz of A/D converter in order to do sampling more than quadruple frequency of transducer frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.386-389
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• 2013

In this paper, for signal integrity analysing high-speed signal between a processor and a DDR2 memory, transient analysis is done and eye diagrams are generated using IBIS models of IC chips and S-parameters of transmission line. From the eye diagrams of such high-speed signals as DQ, DQS/DQSb, Clock, Address and Control, signal quality is assured through measuring timing and voltage margins during setup and hold times and verifying that the over-/under-shoot and the cross points of differential signals satisfy their specifications.

• The Journal of the Korea Contents Association
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• v.16 no.5
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• pp.251-258
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• 2016

Recently, the demand for fast storage devices is rapidly increasing in cloud platforms, social network services, etc. Despite the development of fast storage devices, the traditional Linux I/O stack is not able to exploit the full extent of the performance improvement since it has been optimized for disk-based storage devices. In this paper, we propose an optimized I/O stack which can fully utilize the I/O bandwidth and latency of fast storage devices. To this end, we design a new I/O interface to replace the current block I/O interface and optimize our I/O interface. Our optimized I/O interface bypasses operations/layers in block I/O subsystems of the current Linux I/O stack to fully exploit fast storage devices. We also optimize the Linux file systems such as ext2 and ext4 to run on our I/O interface. We evaluate our I/O stack with multiple benchmarks and the experimental results show that our I/O stack achieves 1.7 times better throughput compared to traditional Linux I/O stack.

• Journal of Korea Game Society
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• v.9 no.5
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• pp.105-115
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• 2009

This article proposes a design and implementation methodology of a gesture-based interface for augmented reality games. The topic of gesture-based augmented reality games is a promising area in the immersive future games using human body motions. However, due to the instability of the current motion recognition technologies, most previous development processes have introduced many ad hoc methods to handle the shortcomings and, hence, the game architectures have become highly irregular and inefficient This article proposes an efficient development methodology for gesture-based augmented reality games through prototyping a table tennis game with a gesture interface. We also verify the applicability of the prototyping mechanism by implementing and demonstrating the augmented reality table tennis game. In the experiments, the implemented prototype has stably tracked real rackets to allow fast movements and interactions without delay.