• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1460-1468
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• 2004

In this paper, we developed a low-area and low-cost SIMD MAC/MAS(Single Instruction Multiple Data Multiply and ACcumulate/Multiply And Subtract) for multimedia that is used much in real life. We compared the result of this research with a previously developed more large and high performance SIMD MAC/MAS. This paper is consist of 5 parts, which are an introduction, the contents of designing SIMD MAC/MAS hardware, a special qualities for previous works, the result of synthesis and conclusion. The design result reduced by size 32% of whole hardware than 64 bit SIMD MAC/MAS block of designed for high performance. This improved ISA (Instruction Set Architecture) to be suitable to embedded DSP(Digital Signal Processor), and shortened bit range of 64-bit data to 32-bit and implement more optimally.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.467-472
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• 2006

This study has been done to design a precise system and develop position control algorithm to control a Composite Smoke Bomb Azimuth driving apparatus of a BLDC servo motor. Having to Blind the sight of opposite tank. the Smoke Bomb Rotational driving system needs instant response that is able to detect opponent appearance and blast the bomb at a short time. So a design that shows fast current response capability or $300[Hz]\sim500[Hz]$ is proposed. in the MIN-MAX PWM technology is used to increase the operational speed. in order to control the blasting position, a precision position control algorithm that utilizes the integral value of speed trajectory is suggested. Also these characteristics are monitored and assessed by the PC based monitoring program which shows the graphs of current, voltage, position, and speed parameters. The main controller is based on a TMS320VC33 high performance floating-point DSP(Digital Signal Process) and the PWM generator utilizes EPM7128 CPLD.

• Journal of the Korea Society of Computer and Information
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• v.16 no.8
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• pp.119-128
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• 2011

This paper introduces design space exploration of many-core processors that meet high performance and low power required by the beamforming algorithm of image signals of mobile ultrasound. For the design space exploration of the many-core processor, we mapped different number of ultrasound image data to each processing element of many-core, and then determined an optimal many-core processor architecture in terms of execution time, energy efficiency and area efficiency. Experimental results indicate that PE=4096 and 1024 provide the highest energy efficiency and area efficiency, respectively. In addition, PE=4096 achieves 46x and 10x better than TI DSP C6416, which is widely used for ultrasound image devices, in terms of energy efficiency and area efficiency, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.3029-3034
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• 2014

The paper describes the scleral diagnostic system implementation for human eyes by using the scleral color code and vessels sign pattern code generations. The system is based on the high performance DSP image signal processor, programmable gain control for preprocessing and RISC SD frames storage. RGB image signals are optimized by PGC, the edge image is detected form the gray image converted. The processing algorithms are executed by scleral color code generation and scleral vessels sign pattern code creation for discriminating and matching. The scleral symptomatic color code is generated by YCbCr values at memory map tolerated and the vessel sign pattern code is created by digitizing the 24 clock and 13 ring zones, overlay matching and tolerances. The experimental results for performance are that the system runs 40ms, and the color and pattern for diagnostic errors are around 20% and 24% on average. The system and technique enable a scleral diagnosis with subdividing the patterns and patient database.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.159-166
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• 2010

For a grid-connected inverter in distributed generation systems, the current control is essential, and recently, the predictive current control based on a high performance digital signal processors (DSP) to satisfy a fast dynamic response has been widely investigated. However, the performance of predictive current control is degraded by the time delay due to digital implementation, the parameter and measured value errors and the interference of noise, and also theses make system even unstable. Therefore, this paper proposes the predictive current control using grid voltage observer for grid-connected inverter applications. To determine the relevant voltage observer gain, the low-order harmonics of grid voltage are considered, and the effect of filter parameter errors is analyzed. The proposed method has a fast current response capability, the robustness to noise and simple implementation due to voltage sensorless control and the robust current control performance to low-order grid harmonics. The feasibility of the proposed method is verified by simulation and experimental results.

• Journal of the Korea Society of Computer and Information
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• v.18 no.8
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• pp.1-8
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• 2013

This paper proposes an effective parallel implementation of a physical modeling synthesis of guitar on the GPU environment. We used appropriate filter coefficients and adjusted the length of delay line for each open string to generate 44,100 six-polyphonic guitar sounds (E2, A2, D3, G4, B3, E4) by using physical modeling synthesis. In addition, we analyzed the physical modeling synthesis algorithm and observed that we can exploit parallelism inherent in the length of delay line. Thus, we assigned CUDA cores as many as the length of delay line and effectively implemented the physical modeling synthesis using GPU to achieve the highest performance. Experimental results indicated that synthetic guitar sounds using GPU were very similar to the original sounds when we compared their spectra. In addition, GPU achieved 68x and 3x better performance than high-performance TI DSP and CPU, respectively. Furthermore, this paper implemented and evaluated the performance of multi-GPU systems for the physical modeling algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.548-555
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• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.7
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• pp.369-375
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• 1999

This paper presents the novel low-performance single-phase voltage regulator which has common arm between the AC/DC and DC/AC power converters and adopts appropriate switching strategy, resulting in the reduction of the number of switching devices. Moreover, by introducing the method to replace the method to replace the conventional AC condenser in filter circuit with the new low-cost type using two DC condenser, the whole voltage regulator system can be more compact, simpler and less expensive than conventional ones. The fully digital controller is designed using high speed DSP, and the proposed system is validated through the experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.127-134
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• 2006

This paper describes a fully hardware realization of vector controller for the permanent magnet synchronous motor (PMSM) using high density field programmable gate mays (FPGA). In the proposed system, the vector controller including vector transformation , PI regulator, position and speed measurement, current measurement, and space vector PWM blocks is implemented in a FPGA using a VHSIC hardware description language (VHDL). The experimental results using a 1.1kW PMSM are provided to show the validity of the proposed system.