• KIPE Magazine
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• v.9 no.2
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• pp.23-25
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• 2004

1980년대 초반까지 대부분의 제어기는 아날로그 형태로 구성되어 복잡한 연산을 수행하기에는 많은 제약이 있었으나, 1980년대 초반부터 일반에게 소개되기 시작한 마이크로프로세서는 과거 불가능하다고 여겨졌던 연산을 현실화하는 계기를 마련하였다. 초기에는 8비트 혹은 16비트 형태의 마이크로프로세서가 주류를 이루었으나. 컴퓨터 및 반도체 분야의 눈부신 발달에 힘입어 80년대 중반에는 32비트 고성능 Digital Signal Processor(DSP)가 출현하게 된다.(중략)

• The Journal of the Acoustical Society of Korea
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• v.22 no.4
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• pp.276-285
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• 2003

In this paper, we present real-time implementation of a R2MFC/DTMF (R2 Multi Frequency Combinations/Dual Tone Multiple Frequency) tone receiver/sender using a high performance DSP (Digital Signal Processor) and apply it to a carrier class VoIP (Voice over Internet Protocol) gateway system. The Receiver utilizes the Goertzel filter and the sender adopts the harmonic resonant filter. We describe, in detail, the techniques of multi-channel real-time implementation on a Texas Instruments TMS320C62x DSP such as effective PCM (Pulse Code Modulation) in/out by means of DMA (Direct Memory Access) and McBSP (Multi Channel Buffered Serial Port) and message communication via HPI (Host Port Interface), etc. From experimental results, we confirmed that the optimized code provided 780 channel capacity at 250㎒ C6202, and the our R2MFC/DTMF receiver/sender met ITU-T (International Telecommunication Union-Telecommunication) specifications.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.99-102
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• 2003

Computing environments of Embedded Systems are different from those of desktop computers so that they have resource constraints such as CPU processing, memory capacity, power, and etc.. Thus, when a desktop S/W is ported into embedded systems, optimization should be seriously considered. In this paper, we investigate several S/W optimization techniques to be considered for porting H.263 encoder into a high performance DSP, TMS320C6711. Through experiments, it is found that optimization techniques employed can make a big performance improvement.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.325-326
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• 2013

전력 시스템과 관련된 연구에서 시뮬레이터는 과도 상태 해석을 위해 필수적이다. 보편적인 디지털 시뮬레이터는 오랜 수행 시간과 저장 메모리의 한계 때문에 대규모 시스템 해석에 부적합하다. 따라서 최근 출시되고 있는 고성능 멀티코어 DSP를 이용하여 실시간 디지털 시뮬레이터를 구현하였다. 구현된 시뮬레이터를 사용하여 선박 통합 전력 시스템을 모의하여 과도 및 정상 상태 해석을 수행하였다.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2551-2553
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• 2000

고속 신호처리 및 실시간 제어 분야에 적합한 제어성능을 발휘하기 위해서는 신호처리전용 마이크로프로세서인 DSP(Digital Signal Processor)를 이용한 제어용 보드가 널리 활용되고 있다. 본 연구를 통하여 전기도금용 전원장치의 고성능화를 위하여 DSP제어용 보드를 개발하였으며, 전체구성은 고속 신호처리를 위한 메인 마이크로프로세서로서 경제성과 응용범위가 넓은 TMS320C32 DSP CHIP, Wait없는 프로그램 및 데이터 처리를 위한 고속 SRAM, 외부 디지털 입출력을 위한 인터페이스 회로, 아나로그 입출력 회로 및 PC 혹은 다른 마이크로컴퓨터와의 통신을 위한 직렬 통신 회로 등으로 구성하였다. 개발된 DSP 보드는 시제품 제작을 완료하여 그 성능 및 신뢰성을 검증하였으며, 전기도금장치의 고성능 제어처리를 위하여 채용하여 상품화 개발을 완료하였다.

• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.648-655
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• 2002

This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.500-506
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• 1999

This paper presents the h밍h performance [GBT type auxiliary jXlWer supply designt.'Cl by new concept. For t the simplification and higher performance, the direct :3 level PWlVl inverter using the high capacity IGBT and t the 32bit DSP are adopted. The cost as well as bulk and weight is appreciably reduced about 40% lower than t those of conventional one. the electrical efficiency above 94~) o and the audible noise level is less than 65dB. In a addition, the TIID(Total lIannonic Distortion) factor is below 5% an이 the voltage fluctuation on a transient s state is below 10%.w 10%.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.4
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• pp.266-273
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• 2010

The main function of the power conditioning system (PCS) is grid-connection with renewable system. The level of total harmonic distortion(THD) caused by the PCS should be maintained less than 5% according to the IEEE-1547 regulation. The THD is measured by the dedicated instrument, not by the PCS in the domestic products. There should be the necessity for harmonic measurement by the PCS in order to cope with degradation or fault condition. In this paper, the real-time harmonic measurement technique using highperformance DSP controller is presented. The proto-system is manufactured using 32-bit floating DSP processor and tested with 256-point DFT(Discrete Fourier Transform) algorithm. The test result shows that the harmonic calculation time is less than 1 [ms]. It can be used as a auxiliary method for predicting the fault in the PCS system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.833-837
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• 2004

The iris image recognition system realization using DSP processor for the faster real-time processing is presented in this paper. The system is composed of CCD camera, DSP processing and network part to link the communication. The system based on high speed DSP processor leads the iris recognition processing time to be faster. The simulation results in 0.9sec below approximately.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.3
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• pp.323-328
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• 2008

This paper presents a Digital Signal Processor achieving high through-put for both decision intensive and computation intensive tasks. The proposed processor employees a multiplier, two ALU and load/store. Unit as operational units. Those four units are controlled and works parallel by superscalar control scheme, which is different from prior DSP architecture. The performance evaluation was done by implementing AC-3 decoding algorithm and 37.8% improvement was achieved. This study is valuable especially for the consumer electronics applications, which require very low cost.