• Journal of IKEEE
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• v.28 no.1
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• pp.33-37
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• 2024

In this paper, we report the design and the measurement of a X-band low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) using a 0.25 ㎛ gate length microstrip GaN-on-SiC high electron mobility transistor (HEMT) technology. The developed X-band GaN-based LNA MMIC achieves small signal gain of 22.75 dB ~ 25.14 dB and noise figure of 1.84 dB ~ 1.94 dB in the desired band of 9 GHz to 10 GHz. Input and output return loss values are -11.36 dB ~ -24.49 dB and -11.11 dB ~ -17.68 dB, respectively. The LNA MMIC can withstand 40 dBm (10 W) input power without performance degradation. The chip dimensions are 3.67 mm × 1.15 mm. The developed GaN-based LNA MMIC is applicable to various X-band applications.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.73-73
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• 2009

트렌지스터의 채널 길이가 줄어듦에 따라 절연층으로 쓰이는 $SiO_2$의 두께는 얇아져야 한다. 이에 따라 얇아진 절연층에서 터널링이 발생하여 누설전류가 증가하게 되어 소자의 오동작을 유발한다. 절연층에서의 터널링을 줄여주기 위해서는 High-K와 같은 유전율이 높은 물질을 이용하여 절연층의 두께를 높여주어야 한다. 최근에 각광 받고 있는 High-K의 대표적인 물질은 $HfO_2$, $ZrO_2$와 $Al_2O_3$등이 있다. $HfO_2$, $ZrO_2$와 $Al_2O_3$는 $SiO_2$보다 유전상 수는 높지만 밴드갭 에너지, 열역학적 안정성, 재결정 온도와 같은 특성 면에서 $SiO_2$를 완전히 대체하기는 어려운 실정이다. 최근 연구에 따르면 기존의 High-K물질에 금속을 첨가한 금속산화물의 경우 밴드갭 에너지, 열역학적 안정성, 재결정 온도의 특성이 향상되었다는 결과가 있다. 이 금속 산화물 중 $HfAlO_3$가 대표적이다. $HfAlO_3$는 유전상수 18.2, 밴드캡 에너지 6.5 eV, 재결정 온도 $900\;^{\circ}C$이고 열역학적 안전성이 개선되었다. 게이트 절연층으로 사용될 수 있는 $HfAlO_3$는 전극과 기판사이에 적층구조를 이루고 있어, 이방성 식각인 건식 식각에 대한 연구가 필요하다. 본 연구는 $BCl_3$/Ar 유도결합 플라즈마를 이용하여 $HfAlO_3$ 박막의 식각 특성을 알아보았다. RF Power 700 W, DC-bias -150 V, 공정압력 15 mTorr, 기판온도 $40\;^{\circ}C$를 기본 조건으로 하여, $BCl_3$/Ar 가스비율, RF Power, DC-bias 전압, 공정압력에 의한 식각율 조건과 마스크물질과의 선택비를 알아보았다. 플라즈마 분석은 Optical 이용하여 진행하였고, 식각 후 표면의 화학적 구조는 X-ray Photoelectron Spectroscoopy(XPS) 분석을 통하여 알아보았다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.48-61
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• 1989

In this paper, two-dimensional numerical simulation of GaAs MESFFT with 0.7${\mu}m$ gate length is perfomed. Drift-diffusion model which consider that mobility is a function of local electric field, is used. As a discretization method, instead of FDM (finite difference method) and FEM (finite element method), the Control-Volume Formulation (CVF) is used and as a numerical scheme current hybrid scheme or upwind scheme is replaced by power-law scheme which is very approximate to exponential scheme. In the process of numerical analysis, Peclet number which represents the velocity ratio of drift and diffusion, is introduced. And using this concept a current equation which consider numerical scheme at the interface of control volume, is proposed. The I-V characteristics using the model and numerical method has a good agreement with that of previous paper by others. Therefore, it is confined that it may be useful as a simulator for GaAs MESFET. Besides I-V characteristics, the mechanism of both velocity saturation in drift-diffusion model is described from the view of velocity and electric field distribution at the bottom of the channel. In addition, the relationship between the mechanism and position of dipole and drain current, are described.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.293-299
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• 2003

In this paper, we have proposed a high conversion and isolation characteristic V-band quadruple sub-harmonic mixer monolithic circuit which is designed and fabricated for the millimeter wave down converter applications. While most of the sub-harmonic mixers use a half of fundamental frequency, we adopt a quarter of the fundamental frequency. The proposed circuit is based on a sub-harmonic mixer with APDP(anti-parallel diode pair) and the 0.1 ${\mu}{\textrm}{m}$ PHEMT's (pseudomorphic high electron mobility transistors). Lumped elements at IF port provide better selectivity of IF frequency and increase isolation. Maximum conversion gain of 0.8 ㏈ at a LO frequency of 14.5㎓ and at a RF frequency of 60.4 ㎓ is measured. Both LO-to-RF and LO-to-IF isolations are higher than 50 ㏈. The conversion gain and isolation characteristic are the best performances among the reported quadruple sub-harmonic mixer operating in the V-band millimeter wave frequency thus far.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.796-805
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• 2000

A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

• Journal of Biomedical Engineering Research
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• v.20 no.1
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• pp.107-113
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• 1999

The purpose of this study was to develop a miniature imaging gamma probe with high performance that can detect small or residual tumors after surgery. Gamma probe detector system consists of NaI(Tl) scintillator, position sensitive photomultiplier tube (PSPMT), and collimator. PSPMT was optically coupled with 6.5 mm thick, 7.62 cm diameter of NaI(Tl) crystal and supplied with -1000V for high voltage. Parallel hexagonal hole collimator was manufactured for characteristics of 40-mm hole length, 1.3-mm hole diameter, and 0.22 mm septal thickness. Electronics consist of position and trigger signal readout systems. Position signals were obtained with summing, subtracting, and dividing circuit using preamplifer and amplifier. Trigger signals were obtained using summing amplifier, constant fraction discriminator, and gate and delay generator module with preamplifer. Data acquisition and processing were performed by Gamma-PF interface board inserted into pentium PC and PIP software. For imaging studies, flood and slit mask images were acquired using a point source. Two hole phantom images were also acquired with collimator. Intrinsic and system spatial resolutions were measured as 3.97 mm and 5.97 mm, respectively. In conclusion, Miniature gamma probe images based on the PSPMT showed good image quality, we conclude that the miniature imaging gamma probe was successfully developed and good image data were obtained. However, further studies will be required to optimize imaging characteristics.

• KIPS Transactions on Computer and Communication Systems
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• v.12 no.6
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• pp.181-188
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• 2023

Block cipher is not expected to be safe for quantum computer, as Grover's algorithm reduces the security strength by accelerating brute-force attacks on symmetric key ciphers. So it is necessary to check the post-quantum security strength by implementing quantum circuit for the target cipher. In this paper, we propose the optimal quantum circuit implementation result designed as a technique to minimize the use of quantum resources (qubits, quantum gates) for SIMECK lightweight cryptography, and explain the operation of each quantum circuit. The implemented SIMECK quantum circuit is used to check the estimation result of quantum resources and calculate the Grover attack cost. Finally, the post-quantum strength of SIMECK lightweight cryptography is evaluated. As a result of post-quantum security strength evaluation, all SIMECK family cipher failed to reach NIST security strength. Therefore, it is expected that the safety of SIMECK cipher is unclear when large-scale quantum computers appear. About this, it is judged that it would be appropriate to increase the block size, the number of rounds, and the key length to increase the security strength.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.