• Annual Conference of KIPS
• /
• 2020.05a
• /
• pp.540-543
• /
• 2020

본 논문에서는 대표적인 이미지 분류 모델인 CNN(Convolutional Neural Network)과 시간에 따른 이미지의 변화를 학습할 수 있는 LSTM(Long Short-Term Memory) 기반의 온라인 서명인식 모델을 제안한다. 실제로는 위조서명을 미리 구하기 어렵다는 사실을 고려해 서명검증 대상자가 아닌 타인의 진서명과 대상자의 일반 필기 데이터를 음의 데이터로서 학습에 사용하였다. 실험 결과, 전체 이미지 중 서명 부분의 비율에 따라 좋은 성능을 보이는 검증 모델이 다르며 Accuracy 성능지표를 통해 이 비율이 높거나 낮을 경우 CNN-LSTM 이, 중간일 경우 CNN 이 적합하다는 것을 확인하였다.

• Annual Conference of KIPS
• /
• 2021.11a
• /
• pp.355-358
• /
• 2021

개인의 신원정보 보호에 대한 중요성이 높아지면서 개인이 직접 자신의 신원정보를 관리하고 데이터의 주권을 신원정보 소유자에게 부여하는 자기주권 신원 시스템에 대한 관심이 높아지고 있다. 자기주권 신원 시스템 내에서 개인은 스스로 자신을 식별할 수 있는 분산 식별자(DID: decentralized identifier)를 생성하고 분산 식별자 별 개인의 자격을 증명해주는 자격증명(VC: verifiable credentials) 정보를 발급받아 개인이 보유하며 자격증명의 검증을 요구하는 검증자에게 선택적으로 자격증명 정보를 제시한다. 개인의 프라이버시를 보호하기 위해 개인의 자격증명을 제시할 때 신원정보의 실제 데이터는 감추고 자격증명의 유효성은 입증시키는 영지식 증명의 개념을 적용하고 있다. 본 논문에서는 영지식 증명 기술을 살펴보고 하이퍼레저 인디(Hyperledger Indy) 기반 자기주권 신원 시스템에서 영지식 증명 기술 도입 예를 보인다.

• Annual Conference of KIPS
• /
• 2023.05a
• /
• pp.156-157
• /
• 2023

메모리 손상으로 인해 발생하는 컴퓨터 시스템의 버그는 아주 오랫동안 지속적으로 발견된 컴퓨터 보안 이슈 중 하나이다. 이에 대한 보호 기법이 많이 제안되었으며 Address Sanitizer(ASAN) 또한 buffer overflow, use-after-free 와 같은 메모리 손상 버그를 보호하기 위한 기술 중 하나이다. 그러나 해당 기술은 소프트웨어적으로만 구현되었고, 충분한 컴퓨팅 자원이 있을 때만 그 유효성과 실용성이 검증되었고 컴퓨팅 자원이 제한된 임베디드 시스템에서의 적용에 대한 연구나 실효성 검증이 부족하다. 이에 본 논문에서는 임베디드 시스템에 ASAN 를 적용하기 위한 코드를 작성하고 성능을 측정하고 분석하였다.

• Transactions of the Korean Society of Pressure Vessels and Piping
• /
• v.20 no.1
• /
• pp.7-15
• /
• 2024

Environmental qualification is required for safety related electrical equipment under harsh environments located in nuclear power plants according to 10 CFR 50.49 and RG 1.89. As analog technology has recently been replaced by digital technology, NRC established RG 1.209 as a regulatory guideline for environmental qualification of safety related computer-based I&C system located in mild environments, requiring evaluation for electromagnetic compatibility, smoke exposure and type test for actual service conditions such as temperature and humidity. In this paper, the trend of environmental qualification for digital equipment is analyzed by comparing the environmental qualification requirements between digital and analog equipment.

• Journal of KIISE:Software and Applications
• /
• v.36 no.7
• /
• pp.523-530
• /
• 2009

Despite the growing need for customized operating system kernels for embedded devices, kernel development continues to suffer from insufficient reliability and high testing cost for several reasons such as the high complexity of the kernel code. To alleviate these difficulties, this study proposes the MOdel-based KERnel Testing (MOKERT) framework for detection of concurrency bugs in the kernel. MOKERT translates a given C program into a corresponding Promela model, and then tries to find a counter example with regard to a given requirement property, If found, MOKERT executes that counter example on the real kernel code to check whether the counter example is a false alarm or not, The MOKERT framework was applied to the Linux proc file system and confirmed that the bug reported in a ChangeLog actually caused a data race problem, In addition, a new data race bug in the Linux proc file system was found, which causes kernel panic.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.34 no.4
• /
• pp.102-109
• /
• 2006

In this paper, the system level EMC radiated emission test results of KoDSat(Korea Demonstration Satellite), its affects upon the Launch vehicle and H/W improving methods regarding its over exceed value of EMC specification are discussed. Regarding its over exceed value, we estimated that DAU of KoDSat generated the exceeded EMC noise source, and these test results were analyzed using the EMC2000 tool to find out how did it affect the FTS(Flight Termination Subsystem) of KSLV-1(Korea Small Launch Vehicle). To diminish the EMC noise source of UHF(430.1Mhz) band level, we redesigned the DAU power board to be applied the various schemes for EMI noise reduction such as grounding, shielding and EMI filtering, and also verified these reworks to analyze its diminishing affects in UHF band level by means of performing the DAU box level EMC test and performing the second KoDSat's system level EMC test.

• Journal of Internet Computing and Services
• /
• v.7 no.1
• /
• pp.121-130
• /
• 2006

In next generation wireless networks, an application must be capable of rating service information in real-time and prior to initiation of the service it is necessary to check whether the end user's account provides coverage for the requested service. However, to provide prepaid services effectively, credit-control should have minimal latency. In an endeavor to support real-time credit-control for Mobile IPv6 (MIPv6), we design an implementation architecture model of credit-control authorization. The proposed integrated model combines a typical credit-control authorization procedure into the MIPv6 authentication procedure. We implement it on a single server for minimal latency. Thus, the server can perform credit-control authorization and MIPv6 authentication simultaneously. Implementation details are described as software blocks and units. In order to verify the feasibility of the proposed model. latency of credit-control authorization is measured according to various Extensible Authentication Protocol (EAP) authentication mechanisms. The performance results indicate that the proposed approach has considerably low latency compared with the existing separated models, in which credit-control authorization is separated from the MIPv6 authentication.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.2
• /
• pp.259-266
• /
• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of Advanced Navigation Technology
• /
• v.27 no.6
• /
• pp.788-797
• /
• 2023

In this paper, we introduced a test environment to test a vision-aided navigation system, as an alternative navigation system when global positioning system (GPS) is unavailable, for vertical take-off and landing (VTOL) unmanned aerial system. It is efficient to use a virtual environment to test and evaluate the vision-aided navigation system under development, but currently no suitable equipment has been developed in Korea. Thus, the proposed test environment is developed to evaluate the performance of the navigation system by generating input signal modeling and simulating operation environment of the system, and by monitoring output signal. This paper comprehensively describes research procedure from derivation of requirements specifications to hardware/software design according to the requirements, and production of the test environment. This test environment was used for evaluating the vision-aided navigation algorithm which we are developing, and conducting simulation based pre-flight tests.

• Journal of KIISE:Software and Applications
• /
• v.36 no.6
• /
• pp.431-442
• /
• 2009

The Software Product Line (SPL) engineering is one of the most promising software development paradigms. With Feature-Oriented Reuse Method (FORM), reusable and flexible components can be built to aid the delivery of various software products such as mobile phone and digital TV applications based on commonalities and variabilities identified during Feature modeling. Model Driven Architecture (MDA) is also an emerging technology which supports developing software products to work on different platforms with platform independent models (PIM). Combining advantages of these two approaches is helpful to build a group of software products which share common Features while working on various platforms. As first step to combine FORM with MDA, we extend UML2.0 with profiles by which FORM architectures and parameterized Statecharts can be modeled. Secondly, we provide rules to examine whether Features are allocated at positions of elements of Statecharts consistently between a Feature model and a parameterized Statechart. Some rules are designed to check the consistency between FORM architectures and parameterized Statecharts. A case study on an elevator control system is provided to demonstrate the feasibility of our modeling approach and consistency checking rules.