• Journal of KIISE
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• v.44 no.1
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• pp.13-20
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• 2017

A message processor is server software that receives various message formats from clients, creates the corresponding threads to process them, and lastly delivers the results to the destination. Considering that each function of an SEDA-based message processor has its own characteristics such as CPU-bound or IO-bound, this paper proposes a thread-mapping strategy called "FC-TM" (function-characteristic aware thread mapping) that schedules the threads to the cores based on the function characteristics in multi-core environments. This paper assumes that message-processor functions are static in the sense that they are pre-defined when the message processor is built; therefore, we profile each function in advance and map each thread to a core using the information in order to maximize the throughput. The benchmarking results show that the throughput increased by up to a maximum of 72 % compared with the previous studies when the ratio of the IO-bound functions to the CPU-bound functions exceeds a certain percentage.

• Journal of the Korean Society for information Management
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• v.39 no.2
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• pp.159-202
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• 2022

The 'National Research Data Platform' and the 'Bio Research Data Platform' were recently built and each is actively creating an ecosystem. It is built independently based on other metadata standards, which may cause future interoperability issues. The purpose of this study is to propose a basis for metadata interoperability between the two platforms. To this end, the metadata standards of each platform were analyzed, crosswork targets were selected and mapped, and the suitability of the mapped elements was verified through experts in the bio field. And more appropriate mapping elements were recommended to derive metadata elements for datasets and files. Through this, it was possible to confirm the possibility that the metadata of each platform could be semantically linked and the basis for securing interoperability.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.9-17
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• 1999

In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.35-46
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm. a given logic equation is constructed as the DAG type. then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also. after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within Cl.B. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time much more than the TMCPLD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• 한국HCI학회:학술대회논문집
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• 2006.02a
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• pp.735-740
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• 2006

유비쿼터스 가정환경에서 서비스를 제공하기 위한 다양한 장치들은 각기 고유한 인터페이스를 가진다. 사용자는 이 장치들을 제어하기 위해서 각각 다른 인터페이스에 익숙해야 하며, 결국 장치 수만큼의 인터페이스를 다루어야 한다. 이와 같은 불편을 해소하기 위해서는 하나의 입력 장치로 여러 장치들을 조작하는 사용자 인터페이스가 필요하다. 특히 유비쿼터스 가정환경에서는 다양한 장치들의 상태 및 기능 등이 동적으로 변하고, 장치가 설정되는 환경도 일정하지 않기 때문에 사용자 중심의 유비쿼터스 환경을 제공하기 위해서는 다양한 인터페이스를 통합할 필요가 있다. 사용자가 비슷하게 인지하는 이종 장치들의 기능을 통합하여 사용자 인터페이스의 동일한 입력으로 매핑한다면 사용자의 부담을 줄일 수 있을 것이다. 본 논문에서는 유비쿼터스 가정환경의 다양한 장비들과 인터페이스 사이의 입출력 관계를 분석하여 시맨틱 네트워크로 모델링하는 방법을 제안한다. 각 장치의 상태와 기능을 시맨틱 네트워크로 정의하고, 노드나 엣지 사이의 유사도를 평가하여 장치와 사용자 인터페이스 사이를 자동으로 매핑한다. 제안하는 방법을 가정환경 입출력장치에 적용하고, 입출력 매핑을 시뮬레이션하는 환경을 구현하여 유용성을 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.225-233
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• 2004

A novel real-time color gamut mapping method is described. The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for digital TV display quality enhancement. The high definition digital TV display devices operate at the clock speed of around 70MHz ～ 150MHz and permit several nano seconds for real-time gamut mapping. Thus, the concept of three-dimensional reduced resolution look-up table is introduced for real-time processing. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in FPGA and ASIC and also successfully adopted in digital TV display quality enhancement purposes.

• Journal of Korean Society for Geospatial Information Science
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• v.5 no.2 s.10
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• pp.193-205
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• 1997

It is required for multi-users to share massive mapping data effectively that distributed data model in the Client-Server environment is developed for the replication consistency. The existing model is not effective to the long transaction just like a mapping system, since it does not account lot consistency between GUI screen and database replications even though it emphasizes on the replication consistency. The performance of concurrency control is very important for those long transactions, especially the mapping systems. This model is to support consistency between GUI screen and replicas using display locks. It suggests consistency model improving process performance by modifying memory consistency model and optimistic concurrency control for mapping data's characteristics.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.19 no.1
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• pp.19-26
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• 2001

The Organizations working with technological projects will be more and more common to connect consultants. Those who shall carry out the pre-analysis of the projects ought to have a professional knowledge to the area about economical methods with information technology and changed technology of surveying and mapping. New surveying and mapping methods, such as TotalStation, GPS, orthophoto, digital map, and satellite remote sensing, have totally changed the old concept of surveying. Also the technology for the new mapping has greatly changed from analog to analytical to digital during the past 50 years. Now, the proper choice of surveying and mapping methods becomes a decision on cost and efficiency rather than the use of a particular technology. As an example, GPS equipment dose cost considerably more than traditional surveying equipment, but the advantages it provides make it very cost-effective. In this study, the cost and benefit factors of the surveying and mapping projects are evaluated independently and benefit/cost ratio(B/C ratio) is used in benefit-cost evaluation of the different surveying methods. The benefit-cost model of surveying and mapping methods will produce economical result in the whole projects.

• Journal of the Korea Computer Graphics Society
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• v.16 no.3
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• pp.41-48
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• 2010

Photon mapping is a traditional global illumination method using many photons emitted from the light source for photo-realistic rendering. However, this method needs a lot of resources to perform tracing of millions of photons. Progressive photon mapping solves this problem. Typical progressive photon mapping performs ray tracing at first to find the hit points on diffuse surface of objects. Next, light source repeatedly emits a small number of photons in photon tracing pass, and power of photons in each sphere that has a fixed radius with the hit points in the center is accumulated. This method requires less resources than previous photon mapping, but it spends much time for gathering enough photons since each of photons progresses through a random direction and rendering high quality image. To improve the method, we propose photon probing that calculates variance of photons in the sphere and controls radius of sphere. In addition, we apply cone filter in radiance estimation step for reducing aliasing at the edges in result image.