• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.1 s.104
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• pp.45-51
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• 2006

In this paper, a new predistortion linearizer for controlling the amplitude of low frequency intermodulation distortion signals is proposed. The low frequency intermodulation distortion(IMD) components are generated by harmonic generator. A vector modulator, modulate fundamental signal with low frequency IMD signals, generates predistortion IMD signals and controls amplitude and phase of them with modulation factors. As a result, this predistorter is suppressed IMD signals of power amplifier effectively. The predistortion linearizer has been manufactured to operate in cellular base-station transmitting band($869{\sim}894\;MHz$). The experimental results show that IMD3 of power amplifier are improved more than 20 dB for CW two-tone signals. Also, it's improved the adjacent channel power ratio(ACPR) more than 10 dB for IS-95 CDMA IFA signals.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.4
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• pp.22-29
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• 2002

Usually, much harmonics are included and cause harmonic loss of motor, torque pulsation, electro-magnetic noise and shock etc. by switching function of inverter when drive induction motor variableness inside. It applied partial resonant Buck converter and three phase voltage type SPWM inverter circuit to induction motor driving system in this paper that see to solve such problem. Changed operation condition variously to do input current of circuit that propose sine-wave by unit power factor almost and capacitor supplied bringing back to life voltage by power supply arranging properly assistance diode and electric power switching. Power factor and efficiency improved as that minimize variation of input at power supply voltage polarity reverse by that add voltage reversal function. Also, by using output filter, reduced harmonic of output line to line voltage components, and introduce state space analysis and forecast operation of rectifier. Such all items confirmed validity through simulation and an experiment.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.5
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• pp.27-35
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• 2000

This paper deals with a control strategy for constant output power of SSRT(Soft Switching Resonant Type) FB(Full Bridge) DC-DC converter by an improved phase shift controller. When the FB DC-DC converter for the high density and the high effect control is operated in high speed switching, the switching loss and switching stress of the switching devices are increased. So, the soft switching method, which has the phase shift control with the digital I-PD controller, must be use in order to reduce its. And the output voltage that controlled by the digital I-PD controller tracks a reference without steady state error in variable input voltage. The validity of control strategy that proposed is verified from simulation results and experimental results by the DSP(TMS320C32).

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.282-291
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• 2001

In this paper, an efficient VLSI architecture of Shape Adaptive Discrete Cosine Transform(SADCT) based on systolic array is proposed. Since transform size in SADCT is varied according to the shape of object in each block, it are dropped that both usability of processing elements(PE´s) and throughput rate in time-recursive SADCT structure. To overcome these disadvantages, it is proposed that the architecture based on a systolic way structure which doesn´t need memory. In the proposed architecture, throughput rate is improved by consecutive processing of one-dimensional SADCT without memory and PE´s in the first column are connected to that in the last one for improvement of usability of PE. And input data are put into each column of PE in parallel according to the maximum data number in each rearranged block. The proposed architecture is described by VHDL. Also, its function is evaluated by MentorTM. Even though the hardware complexity is somewhat increased, the throughput rate is improved about twofold.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.6
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• pp.26-37
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• 2001

In order to improve the several problems of the general backpropagation, we propose a method using a fuzzy logic system for automatic tuning of the activation function gain in the backpropagation. First, we researched that the changing of the gain of sigmoid function is equivalent to changing the learning rate, the weights, and the biases. The inputs of the fuzzy logic system were the sensitivity of error respect to the last layer and the mean sensitivity of error respect to the hidden layer, and the output was the gain of the sigmoid function. In order to verify the effectiveness of the proposed method, we performed simulations on the parity problem, function approximation, and pattern recognition. The results show that the proposed method has considerably improved the performance compared to the general backpropagation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1701-1713
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• 1993

This paper proposes a simple and highly effective RACMC(Real-time ATM Cell Monitoring and Control) algorithm and the resulting bandwidth gain effects art considered. RACMC algorithm performs usage parameter controls according to the monitoring informations of input data cells generated from the accepted connections and the controlling informations set by the M/P(Management Plane) for that connection. The results of monitoring and controlling actions for ATM data cells are transmitted to the M/P and the control parameters in lookup table are updated according to the condition of currently used bandwith. Therefore, the proposed algorithm can allocate network resource optimally and solve the several tantalizing problems that the existing cell control algorithm have, that is, the difficulty in controlling as monitoring very bursty traffics, unavoidable processing delay, and limited input buffer size when implemented. By the performance analysis using computer simulation, RACMC algorithm proves to be very effective especially in ATM network as implemented simply.

• KIPS Transactions on Software and Data Engineering
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• v.8 no.4
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• pp.145-152
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• 2019

Unlike a single value from a sensor device, a massive data set has characteristics for various processing aspects; input data may be formed in a different format, the size of input data varies, and the processing time of analyzing input data is not predictable. Therefore, context aware systems may contain complex modules, and these modules can be implemented and used in different ways. In order to solve these problems, we propose a method to handle context information from the result of analyzing massive data. The proposed method considers analysis work as a different type of abstracting context and suggests the way of representing context information. In experiment, we demonstrate how the context processing engine works properly in a couple of steps with healthcare services.