• Journal of IKEEE
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• v.20 no.3
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• pp.273-278
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• 2016

In HEVC variable block size motion estimation, same search window data are duplicatedly used in each block size. It increases memory bandwidth, and it is difficult to exploit early termination. In this paper, largest block size and its corresponding smaller block sizes with same positions are performed at the same time. It reduces memory bandwidth and computation by reusing search window data and computation results. In the early termination, image quality can be degraded when it determines early termination by observing largest block size only, since smaller block sizes cannot be equally terminated due to their relative positions. So, in this paper, processing order of early termination is changed to perform smaller block sizes in turns. The designed motion estimation engine was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 36,101 gates and 263.15 MHz, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.454-463
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• 2010

After the efficiency of H.264 video compression has been announced, it replaced MPEG-2 standard in several applications. So transcoding methods of MPEG-2 to H.264 have been studying because there are variety devices and contents followed by MPEG-2. Although H.264 supported various service such as IPTV, DMB, digital broadcasting etc, but users using MPEG-2 devices cannot accessible to them. This paper propose H.264 to MPEG-2 transcoding for users of MPEG-2 devices without displacement H.264. The proposed method predicted a motion vector for MPEG-2 encoder after it extracted from motion vectors of variable blocks in H.264 to improve processing time. Also it predicted a optimal motion vector using modified boundary matching algorithm after grasped a special character for boundary and background of object. The experimental results from proposed method show a considerable reduction in processing time, as much as 68% averagely, with a small objective quality reduction in PSNR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.48-54
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• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.997-1003
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• 2007

H.264/AVC enhances inter-frame coding performance adopting new intra and inter mode prediction in inter-frame motion prediction. H.264 encoder provides performance superior to existing standards with the prediction modes. Instead of enhanced performance, however, both predictions increase complexity of encoder and demand a lot of coding time. This paper proposes a method using local statistics of resultant intra mode, my and mode map to predict inter mode. There are relationship between intra and inter mode, and we can predict inter mode using neighboring macroblocks' resultant mode and motion vector according to the contents of frame. The experimental results show that the proposed algorithm reduces encoding time by 31% on average with a negligible loss of PSNR and bitrate.

• The Transactions of the Korea Information Processing Society
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• v.4 no.4
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• pp.1121-1131
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• 1997

In video coding at high compression rate, factal compression schemes in spatial domain have outstanding blocking artifacts and compression schemes in wavelet transform domain have rinfing artifacts at edges. In order to compensate these disadvantages, we propose a fractal video coding in wavelet transrorm domain which leads to clear edges without blocking atrifacts even at high bompression rate. The proposed method performs variable block sized motion estimation by using correlation among different subbands. Then the wavelet coefficients which are not enoded dffectively by the motion estimation are compressed by inter-frame fractal coding which predicts fine scale subbands hierarchically from the next coarser scale subbands. Computer sumulations with sev-eral test images wequences show that the proposed method shows better performance than the conventional video coding methods using fractal and wavelet.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.801-812
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• 2005

H.264/AVC is the international video coding standard which has significant improvements of coding efficiency. ITU-T(International Telecommunication Union-Telecommunication standardization sector) and MPEG(Moving Picture Experts Group) adopts various complex coding tool such as variable block size motion, multiple reference frames, quarter-pel motion estimation/compensation (ME/MC) and rate-distortion(RD) optimization, etc. H.264 reference model employs complex mode decision technique based on RD optimization which requires high computational complexity. In this paper, we propose an efficient coding mode decision based on the cost distribution of RD in the macroblock coding mode sequence. Simulation results show that the proposed method reduces encoding time by 34% on average and save the number of computing RD cost by 82%.

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1359-1365
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• 2008

The portion of header in H.264 gets higher than those of previous standards instead of its better compression efficiency. Therefore, this paper proposes a new technique to compress the header of H.264. Unifying a sentence elementary in H.264, H.264 does not consider the distribution of element which be encoded and uses existing Exp-Golomb method, but it is uneffective for variable length coding. Most of the header are block type(s) and motion vector difference(s), and there are redundancies in the header of H.264. The redundancies in the header of H.264 which are analyzed in this paper are three. There are frequently appearing symbols and non-frequently appearing symbols in block types. And when mode 8 is selected in macroblock, all of four sub-macroblock types are transferred. At last, same values come in motion vector difference, especially '0.' This paper proposes the algorithm using type code and quadtree, and with them presents the redundant information of header in H.264. The type code indicates shape of the macroblock and the quadtree does the tree structured motion compensation. Experimental results show that proposed algorithm achieves lower total number of encoded bits over JM12.4 up to 32.51% bit reduction.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.104-115
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• 1993

The motion compensated coding (MCC) technique, which exploits the temporal redundancies in the moving images with the motion estimation technique,is one of the most popular techniques currently used. Recently, a variable block size(VBS) motion estimation scheme has been utilized to improve the performance of the motion compensted coding. This scheme allows large blocks to the used when smaller blocks provide little gain, saving rates for areas containing more complex motion. Hence, a new VBS motion estimation scheme with a hierarchical structure is proposed in this paper, in order to combine the motion vector coding technique efficiently. Topmost level motion vector, which is obtained by the gain/cost motion estimation technique with selective motion prediction method, is always transmitted. Thus, the hierarchical VBS motion estimation scheme can efficiently exploit the redundancies among neighboring motion vectors, providing an efficient motion vector encoding scheme. Also, a restricted search with respect to the topmost level motion vector enables more flexible and efficient motion estimation for the remaining lower level blocks. Computer simulations on the high resolution image sequence show that, the VBS motion estimation scheme provides a performance improvement of 0.6~0.7 dB, in terms of PSNR, compared to the fixed block size motion estimation scheme.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.2
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• pp.138-148
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• 2001

Digital Video (DV) coding standards for digital video cassette recorder are based mainly on DCT and variable length coding. DV has low hardware complexity but high compressed bit rate of about 26 Mb/s. Thus, it is necessary to encode video with low complex video coding at the studios and then transcode compressed video into MPEG-2 for video-on-demand system. Because these coding methods exploit DCT, transcoding in the DCT domain can reduce computational complexity by excluding duplicated procedures. In transcoding DV into MPEC-2 intra coding, multiplying matrix by transformed data is used for 4:1:1-to-4:2:2 chroma format conversion and the conversion from 2-4-8 to 8-8 DCT mode, and therefore enables parallel processing. Variance of sub block for MPEG-2 rate control is computed completely in the DCT domain. These are verified through experiments. We estimate motion hierarchically using DCT coefficients for transcoding into MPEG-2 inter coding. First, we estimate motion of a macro block (MB) only with 4 DC values of 4 sub blocks and then estimate motion with 16-point MB using IDCT of 2$\times$2 low frequencies in each sub block, and finish estimation at a sub pixel as the fifth step. ME with overlapped search range shows better PSNR performance than ME without overlapping.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1589-1596
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• 2010

In this paper, we propose the method that reduce computational complexity for intermode decision using CBP(coded block pattern) and coded information of colocated-MB(macro block). Proposed method classifies MB into best-CBP and normal-CBP according to the characteristics of CBP. On best-CBP, it eliminates the computation for $8{\times}8$ mode on intermode decision process because the probability for SKIP mode and M-Type mode is 96.3% statistically. On normal-CBP, it selectively eliminates the amount of computation for bit-rate distortion cost, because it uses coded information of colocated-MB and motion vector cost in deciding SKIP mode and M-Type mode. The simulation results show that the proposed method reduces total coding time to 58.44% in average, and is effective in reducing computational burden in videos with little motion.