• Title/Summary/Keyword: 가변 레이아웃

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A Study on the Application of Responsive Web for the Flexible Box (플렉서블 박스의 반응형 웹 적용에 대한 연구)

  • Kim, Ho Jin;Kim, Chang Soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.1093-1094
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    • 2015
  • Due to the use of the responsive web, representation of the web in a variety of devices is to be implemented in a more unified look. In this paper, we suggest how to implement fluid layout. We explain how to configure the fluid layout with the latest technology, flexible box and confirmed its advantages and disadvantages. In addition, we propose ways to solve the problem occurred by applying the flexible box.

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An Adaptive Equalizer with the Digitally Controlled Active Variable Capacitor (디지털 능동형 가변 축전기를 사용한 적응형 이퀄라이저)

  • Lee, Won-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.11 no.11
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    • pp.1053-1060
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    • 2016
  • This paper proposes an adaptive equalizer with the digitally controlled active variable capacitor. An equalizing amplifier consists of a main amplifier and a source degeneration RC filter which is implemented using the digitally controlled active variable capacitor for area efficiency and linear loss compensation. The active capacitor changes its capacitance by the amplifier gain control, which is based on miller effect. In the simulated results, the proposed equalizer compensates the high frequency loss and extends the data eye width from 0.31 UI to 0.64 UI.

Statistically Optimized Asynchronous Barrel Shifters for Variable Length Codecs (통계적으로 최적화된 비동기식 가변길이코덱용 배럴 쉬프트)

  • Peter A. Beerel;Kim, Kyeoun-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.11A
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    • pp.891-901
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    • 2003
  • This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.

Context-aware Mobile system for Augmentative and Alternative Communication (보완대체 의사소통도구를 위한 상황인식 모바일 시스템)

  • Park, DongGyu;Kim, Young-Joo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.7
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    • pp.1740-1746
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    • 2013
  • Augmentative and alternative communication(AAC) is a communication tool for those with impairments or restrictions on the production or comprehension of spoken language. Traditional AAC has used a portable board with pictures and texts with which disabled person could be supported by it. Currently, smart phone based AAC researches and developments are actively studying. With emerging concepts of context-aware computing, the mobile devices can provide mobile users with timely information and location based services. We proposed a adjustable AAC system for disabled people of which has variable layouts and selectable items. We also implemented context-ware application for AAC systems including time, location and click count informations on smart phone. The system can adaptively change its layout and select AAC items depending on various situation of disabled persons.

CMOS Integrated Fingerprint Sensor Based on a Ridge Resistivity (CMOS공정으로 집적화된 저항형 지문센서)

  • Jung, Seung-Min
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.571-574
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    • 2008
  • In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

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Fingerprint Sensor Based on a Skin Resistivity with $256{\times}256$ pixel array ($256{\times}256$ 픽셀 어레이 저항형 지문센서)

  • Jung, Seung-Min
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.3
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    • pp.531-536
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    • 2009
  • In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

High-Speed Pipelined Memory Architecture for Gigabit ATM Packet Switching (Gigabit ATM Packet 교환을 위한 파이프라인 방식의 고속 메모리 구조)

  • Gab Joong Jeong;Mon Key Lee
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.11
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    • pp.39-47
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    • 1998
  • This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

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A Study on Development of Responsive Web and Hybrid App using Bootstrap (부트스트랩을 이용한 반응형 웹 및 하이브리드 앱 개발)

  • Heo, Neung-Ho;Kim, Hyeong-Eun;Choi, Byung-Jun;Kim, Young-Jin;Kim, Yong-Hoon;Suh, Tae-Weon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2016.10a
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    • pp.738-741
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    • 2016
  • 다양한 크기의 모바일 기기가 등장함에 따라 기존 웹 어플리케이션으로는 개발자가 의도한대로 레이아웃을 구성하기 어려우며 네이티브 어플리케이션은 운영체제별로 각각 개발해야하기 때문에 많은 개발 시간을 필요로 한다는 단점이 있다. 본 논문에서는 부트스트랩을 이용하여 기기의 화면 크기에 가변적인 반응형 웹을 구축하고 모바일 운영체제의 웹뷰를 이용한 하이브리드 앱을 구현함으로써 개발과정 및 개발 시간 단축을 검증하였다.

A Design and Implementation of Smartphone-Based AAC System (스마트폰 기반 보완 의사 대체 시스템의 설계와 구현)

  • Ghatkamble, Rajlakshmi;Son, JinHan;Park, DongGyu
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.8
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    • pp.1895-1903
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    • 2014
  • Smartphone have become the very important devices in our daily life and provide various roles on impairment and communications of developmental disabilities, acquired neurogenic disorders and autisms. Due to the growth of the technology, an Augmentative and Alternative Communication (AAC) also meets needs and wants, including user customization, configurable layouts and registration of new core vocabulary for individual users. This paper describes the research conducted to design the smartphone-based AAC system. This AAC comprises of a form of communication types such as picture communication boards and sophisticated computer and mobile based devices that can speak in the phrases and sentences for their users. We deployed our AAC system on various sports situations using smartphone systems and also provided user customization method for AAC user's disability levels.

The Design of carry increment Adder Fixed Fan-out (팬 아웃이 고정된 carry increment 덧셈기 설계 방법)

  • Kim, Yong-Eun;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.44-48
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    • 2008
  • According to increment of stage, the speed of changeable stage Carry-increment adder can be close to $O(\sqrt{2n})$ because the word length which is computed in stage can be lengthened by 1 bit. But the number of stage bits is increased, fan-out of carry which is inputted in stage is increased. So tile speed can be slow. This paper presents a new carry-increment adder design method to fix the number of fan-outs regardless of the number of stages. By layout simulation of 37-bit adder, the area can be Increased up to 40%, but speed improvement up to 75% can be achieved, by the proposed method, compared with a conventional method.