• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.206-212
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• 2006

Many image and video compression algorithms work by splitting the input image into blocks and producing variable-length coded bits for each block data. If variable-length coded data are transmitted consecutively, then the resulting coder is highly sensitive to channel errors. Therefore, most image and video techniques for providing some protection to the stream against channel errors usually involve adding a controlled amount of redundancy back into the stream. Such redundancy might take the form of resynchronization markers, which enable the decoder to restart the decoding process from the known state, in the event of transmission errors. The Error Resilient Entropy Code (EREC) is a well known method which can regain synchronization without any redundant information to convert from variable-length code to fixed-length code. This paper proposes an enhancement to EREC, which greatly improves its transmission ability for the compressed image quality without any redundant bits in the event of errors. The simulation result shows that the both objective and subjective quality of transmitted image is enhanced compared with the existing EREC at the same BER(Bit Error Rate).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.921-930
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• 2004

In this paper, a robust video transmission system is proposed. To effectively prevent the corruption of video stream and its propagation in spatial and temporal domains, a version of turbo code, so-called as byte-aligned variable-length turbo code, is applied. Protection performance of the proposed turbo code is first evaluated by applying it to GOB-based variable-size ITU-T H.263+ video packets, where the protection level is statically controlled based on the joint source-channel criteria. This protection is then extended to support the adaptation of code ratio to best match the time-varying channel condition. The time-varying Rayleigh fading channel is modelled considering the correlation of the fading channel. The resulting performance comparison with the static turbo code as well as the conventional RCPC code clearly demonstrates the possibility of the proposed adaptation approach for the time-varying correlated Rayleigh-fading channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• Journal of IKEEE
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• v.12 no.2
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• pp.118-123
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• 2008

The Khronos group releases OpenGL ES 2.0 API specification bringing streamlined shader programming to graphics processor of embedded system. For this reason, the mobile devices have need of graphics processor for supporting a OpenGL ES 2.0 API. We need to extend instruction`s length to support OpenGLES 2.0 API, so it needs more memory size. In this paper, we propose a new instruction format that offers availability for use the instructions. This proposed instruction adopt a variable length method and unit instruction architecture. This proposed instruction architecture that support to OpenGLES 2.0 API has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2691-2697
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• 2010

Shader instructions and Compiler are designed for supporting 3D graphic shader 3.0 API. Variable-length instructions are proposed to reduce the size of hardware of graphic processor in SIMD structure by shortening the length of instructions. The designed shader compiler supports variable and two phased structured instructions, and can be programmable at ESSL level. Conformance Test proposed by Khronos group is accomplished to verify the design result of instructions and complier. The test result shows overall average 37% performance improvement at the 16 functions of basic GL shader.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.2
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• pp.133-138
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• 1987

In this paper the tuning characteristics of resonant frequencies are experimentally studied through the variation of the length of the inner conducting rod in a re-enterant eavity resonator. The re-enterant eavity resonator consists of a coaxial cable and a cylindrical wave guide. The length of the inner conducting rod can be varied to the longitudinal direction. The resonant frequencies of TMonq modes are measured according to the arbitrary length. In order to verify the propriety of experimental results, experimental results are compared with other theoretical results. The results in this paper can be applied to wave meter and resonant circuit of amplifier. They will be use to vary resonant frequencies of a dielectric resonator in MIC and filter.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.244-246
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• 2002

최근 무선 인터넷과 핸드폰, PDA, HPC 등과 같은 모바일 장치의 발전으로 인하여 이동체의 위치를 중심으로 하는 LBS가 점차적으로 많은 분야에서 사용되고 있다. 이동체의 위치 데이타는 GPS와 같은 위치 측정 시스템을 이용하여 대용량으로 발생하게 되는데 기존의 정적인 데이타를 처리하기 위한 GIS를 사용하여 이러한 데이타를 처리하는 것은 비효율적이다. 그러므로, 본 논문에서는 이러한 동적인 데이타를 효과적으로 처리할 수 있는 LBS를 위한 실시간 GIS 엔진을 설계 및 구현하였다. 본 논문에서의 실시간 GIS 엔진은 LBS에서 필요한 공간, 비공간, 위치 데이타를 효과적으로 관리할 수 있다. 실시간 GIS 엔진은 인터페이스 관리자, 질의 관리자, 인덱스 관리자, 데이타 로더, 레이어 관리자, 위치 데이타 관리자, 메타 데이타 관리자, 객체 관리자로 구성되어 있으며 기존의 HP 실시간 데이타베이스 시스템에 공간 데이타 타입, 공간 연산자, 가변 길이 데이타 처리, 테이블 자동 확장 기능 등을 추가하여 LBS에서 사용되는 대용량 가변 길이 데이타를 효과적으로 처리할 수 있도록 하였다.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.234-235
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• 2000

1.55$mu extrm{m}$의 파장 영역에서 동작하는 파장 가변 단일 주파수 레이저는 파장 분할 방식(WDM) 광통신 시스템, 분광학 또는 광센서 등에서의 응용 가능성을 가지고 있다. 특히, 파장 가변 단일 주파수 광섬유 레이저는 선폭이 좁고, 세기 잡음이 작으며, 출력 파워가 큰 한편, 광섬유로의 집적이 간단하다는 등의 장점을 가지고 있어 이에 관한 많은 연구가 이루어지고 있다. 본 논문에서는 주파수 변환기와 광섬유 흡수 격자를 이용하여 긴 길이의 선형 공진기에서 구현된 파장 가변 단일 주파수 어븀 첨가 광섬유 레이저의 동작에 관하여 기술하였다. (중략)