• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.3
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• pp.14-20
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• 2002

Recently, miniaturization and mass production are the main trends in manufacturing fields. Therefore, ultraprecision machining and MEMS technology have been taken more 7md more important position in machining of microparts. Micro endmilling is one of the prominent technology that has wide spectrum of application field ranging from duo parts to micro products, such as PDP md IT components, in precision products manufacturing. However, decreasing of burr is significant problem in making smooth and precise parts in micro endmilling. This paper shows removal characteristics of burr generated by micro endmilling process. This results satisfies micro endmilling for micro barrier ribs of heights is $50{\mu}m$, $100{\mu}m$, $200{\mu}m$, $300{\mu}m$, and observation from of burr. Additionally, it is necessary to understand the formation mechanism of burr of micro barrier ribs to iud proper decreasing method.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.447-449
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• 2006

본 논문에서는 변압기를 이용한 새로운 PDP용 전력회수회로를 제안한다. 2권선형 변압기를 이용하여 패널에 저장된 에너지를 전원으로 회생시켜 방전 이외의 용량성 부하로 기인하는 전력손실을 최소화 한다. 제안된 회로는 주스위치의 영전압 스위칭과 보조 스위치의 영전류 스위칭이 가능하고 변압기를 이용하기 때문에 권선비에 의한 자유로운 공진에너지 조절이 가능한 장점을 갖는다. 변압기 이용으로 인해 영전압 및 고속구동을 위한 천이시간 증가시 전류주입모드와 전압인가모드를 동시에 사용할 수 있는 장점을 갖는다. 제안된 회로의 성능과 하이브리드 모드 구동시에 나타나는 장점을 42인치 PDP적용실험을 통해 검증해본다.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.554-557
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• 2002

In this paper, PDP driving circuit is designed to show the pattern of still-image with ADS (Address Display Separation) driving method. The designed circuits consist of three stages which are the image processing program, digital logic parts, and power circuits. The Image processing program is designed serial-communication with RS-232C using BASIC language. Digital logic parts design ADS driving signals with Xilinx FPGA and are simulated by ModelSim 5.5f. Power circuits convert output of digital logic parts into high voltage which panel is drived.

• Journal of the Semiconductor & Display Technology
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• v.5 no.3 s.16
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• pp.33-36
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• 2006

To produce a fine structure with uniform surface of barrier ribs in PDP, acid etching process has been used in manufacture process. It is necessary to understand the mechanism of etching, particularly on the interface of ceramic fillers and matrix glass. We investigated the effect of ceramic fillers (ZnO, $Al_2O_3$) on the microstructure of borate glass system to find an etching mechanism of barrier ribs. The barrier ribs was etched with several steps, dissolving a small amount of residual glass, taking out alumina fillers, and removing a cluster type of ZnO fillers and glass matrix.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.200-204
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• 2006

본 연구에서는 새로 고안된 NOT-AND 논리에 의한 방전 논리 gate PDP의 입력 DC 방전특성에 대해 고찰하고 동작특성을 해석하였다. 새로 고안된 방전 AND gate는 방전 경로에 따른 전극사이의 전위차의 변화로 AND 출력을 유도한다. 이러한 방전 논리 소자를 가지는 PDP에서는 직류방전이 논리게이트의 역할을 한다. 실험결과 이 DC 입력방전을 위해 priming 방전을 인가한 경우가 인가하지 않은 경우에 비해 방전지연시간이 1/3로 단축되며 방전개시전압은 1/2로 감소하였다. 또한 이 priming 방전은 방전종료후 $30{\mu}s$ 정도까지 영향을 미친다. 그리고 이 직류방전의 시간적, 위치적 방전특성을 측정한 결과, 방전에 따른 시간적 거리의 변화는 상당한 영향을 미치나 인접 전극들의 위치적인 영향은 거의 미미하다는 결론을 얻었다.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.05a
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• pp.113-116
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• 2009

Full-HD 구현이 가능하고, 패널 전체에 priming 방전을 동시에 일으킬 수 있는 새로운 고속구동법인 표시기간 중첩 프라이밍 방전 기술의 초기화 펄스 특성을 연구하였다. ramp 펄스를 이용한 약방전으로 초기화 방전을 일으킬 경우 램프 기울기가 작아질 수록 불필요한 광을 줄일 수 있어 명암비가 높아지므로 프라이밍 펄스폭을 증가시키는 것은 매우 중요한 일이다. 본 논문에서는 ramp의 기울기를 변화시키며 안정적인 표시방전이 유지되는 ramp 펄스폭을 실험을 통해 확인하였고, 그 결과 $200{\mu}s$(ramp 기울기 $1.45V/{\mu}s$)의 ramp 펄스폭에서도 표시방전이 안정적으로 발생한다는 것을 알았다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.284-287
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• 2000

We analyzed the 3-dimensional discharge characteristic in plasma display panel(PDP) cell using the 3-dimensional emission distribution of 828nm light measured by scanned point detecting method(SPDM). The emitted light distributions on the ITO electrode show the stronger light intensity near to the electrode gap than outside. Also, 828nm light is widely detected outside of the bus electrode. We consider that measurement using new SPDM is effective to analyze the discharge physics and propose the new panel structures.

• Korean Chemical Engineering Research
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• v.47 no.2
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• pp.150-156
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• 2009

Plasma Display Panels(PDPs) require to have improved luminous efficiency, low manufacturing cost, and high image quality to compete with other flat display devices such as Liquid Crystal Displays(LCDs) and organic light-emitting diodes(OLEDs). In addition, the diversity of product line-up may be needed for high market share. In this paper, the optical characteristics of typical green phosphor for PDP application are reviewed and the problem-based solution will be proposed. We also shortly describe the principle of 3D-PDPs which are promising. Then, the requirement of green phosphor for 3D-PDP application is summarized and research achievement, as of now, is described. The typical problems of $Zn_2SiO_4:Mn$ phosphor, which is the most well-known, are the negatively charged surface property and the long decay time, which leads to unstable discharge in green cell and afterimage. These problems were solved by coating the phosphor surface with metallic oxide. It was found that $Al_2O_3$ would be the best material for $Zn_2SiO_4:Mn$ phosphor. It gives longevity as well as low operating voltage due to the charging effect in green cells. Also, new phosphors, $(Y,\;Gd)Al_3(BO_3)_4:Tb$ and $(Mg,\;Zn)Al_2O_4:Mn$ phosphor are proposed for increasing the luminance and reducing the decay time, which are capable to apply for 3D-PDP application.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.33 no.11
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• pp.886-893
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• 2009

To develop glass panel vacuum lift system for the post process in module line of FPD(Flat panel display) such as LCD and PDP, new vacuum adsorption parts of this system are proposed. These parts are composed of variable geometry configurations utilizing ceramic porous medium for variable size of glass panels. In order to design this device, detail understanding of flow phenomena in the flow path of vacuum adsorption system is essential. Thus, CFD analysis and designs are performed for several configurations in terms of pressure drop and balancing force at the adsorption side. From the result, new configuration is recommended for optimum design and manufacturing purpose.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.135-139
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• 2015

The address discharge time lags are investigated in each subfield time in AC plasma display panel and a modified driving waveform is proposed to reduce the address discharge time lag by applying different additional scan voltage under no misfiring discharge production. The weak plasma discharge in AC PDP is generated by applying high positive-going ramp waveform to the scan electrode during the first reset period and that induce the production of the priming particle and wall charge. Because the wall charge becomes the wall voltage in a cell, the wall plus external address voltage produce the address discharge. However, as the wall charge in a cell is gradually disappeared as time passed, the address discharge time in the subfield time for 1 TV frame is lagged. In the first subfield time, the address discharge is faster produced than the other subfield time because the wall charge are much remained by the high positive-going ramp voltage during the reset period in the first subfield time. Meanwhile, from the second to last subfield, the address discharge production time is gradually delayed due to the dissipation of the wall charge in a cell. In this study, the address discharge time lags are measured in each subfield time and the total address discharge time lags are shortened by applying the different additional scan voltage during the address period in each the subfield time.