• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.86-89
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• 2004

Organic thin film transistors (OTFTs) are fabricated on the plastic substrate through 4-level mask process without photolithographic patterning to yield the simple fabrication process. And we herewith report for the effect of dielectric surface modification on the electrical characteristics of OTFTs. The KIST-JM-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide $(ZrO_2)$ gate dielectric layer. In this work, we have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2001.06a
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• pp.13-13
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• 2001

현재 초고속 가공 공구의 국내 시장은 150억원이며 향후 3년 내에 1500억원으로 급성 장활 전망이다. 무윤활 초고속 가공을 실현하기 위해서는 윤활특성이 우수한 초고경도 코팅의 개발이 필요하며 이를 통해 기계설비의 수명향상과 폐유문제 해결을 기대할 수 있다. 기존의 고체윤활 코팅은 초고경도 코팅의 상부에 $MoS_2$, Graphite 등 윤활성 박막을 합성하였으나, 이들은 Hexagonal 구조의 연질 박막이며 수분이 존재하는 대기중에서는 윤활 및 내마모 특성이 급격히 저하된다. 환경친화 대체소재 개발의 일원으로 TiN, ZrN 박막 등이 이미 개발되었고 기계적 특성이 우수하여 널리 응용되고 있으나 아직 경도(약 20GPa 내외) 및 윤활성의 한계 (마찰계수 $\mu=O.6$)를 극복하지 못하고 있다. TiN박막 위의 Cu의 첨가는 TiN의 구조와 성질을 크게 변화시키는 것으로 알려져 있다. 따라서 본 연구에서는 TiN 기지 위에 Cu를 도핑함으로써 경도의 상승을 통환 내구력의 향상과 마찰계수의 감소를 통한 윤활성의 향상을 보고자하였다. TiN합성의 안정화를 위하여 magnetron sputtering과 arc ion pIatingd을 병용한 hybrid 공정을 이용하였다. Cu첨가에 따른 결정 성장 거동의 변화를 보기 위해 XRD 분석을 실행하였고, EDS 분석을 통해 Cu target 전류밀도에 의한 기지내의 Cu의 함량변화를 고찰하였으며, 경도 및 윤활특성을 고찰하기 위해서 경도 시험과 마모 시험(ball-on disc type test)를 하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.100-100
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• 2011

2004년 일본의 Hosono 그룹에 의해 처음 발표된 이래로, amorphous gallium-indium-zinc oxide (a-GIZO) thin film transistors (TFTs)는 높은 이동도와 뛰어난 전기적, 광학적 특성에 의해 큰 주목을 받고 있다. 또한 넓은 밴드갭을 가지므로 가시광 영역에서 투명한 특성을 보이고, 플라스틱 기판 위에서 구부러지는 성질에 의해 플랫 패널 디스플레이나 능동 유기 발광 소자(AM-OLED), 투명 디스플레이에 응용될 뿐만 아니라, 일반적인 Poly-Si TFT에 비해 백플레인의 대면적화에 유리하다는 장점이 있다. 최근에는 Y2O3나 ZrO2 등의 high-k 물질을 gate insulator로 이용하여 높은 캐패시턴스를 유지함과 동시에 낮은 구동 전압과 빠른 스위칭 특성을 가지는 a-GIZO TFT의 연구 결과가 보고되었다. 하지만 투명 디스플레이 소자 제작을 위해 플라스틱이나 유리 기판을 사용할 경우, 기판 특성상 공정 온도에 제약이 따르고(약 $300^{\circ}C$ 이하), 이를 극복하기 위한 부가적인 기술이 필수적이다. 본 연구에서는 p-type Si을 back gate로 하는 Inverted-staggered 구조의 a-GIZO TFT소자를 제작 하였다. p-type Si (100) 기판위에 RF magnetron sputtering을 이용하여 Gate insulator를 증착하고, 같은 방법으로 채널층인 a-GIZO를 70 nm 증착하였다. a-GIZO를 증착하기 위한 sputtering 조건으로는 100W의 RF power와 6 mTorr의 working pressure, 30 sccm Ar 분위기에서 증착하였다. 소스/드레인 전극은 e-beam evaporation을 이용하여 Al을 150 nm 증착하였다. 채널 폭은 80 um 이고, 채널 길이는 각각 20 um, 10 um, 5 um, 2 um이다. 마지막으로 Furnace를 이용하여 N2 분위기에서 $500^{\circ}C$로 30분간 후속 열처리를 실시한 후에, 전기적 특성을 분석하였다.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.9
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• pp.931-935
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• 2012

In this study, we fabricate and investigate low-temperature solid oxide fuel cells with a ceramic substrate/porous metal/ceramic/porous metal structure. To realize low-temperature operation in solid oxide fuel cells, the membrane should be fabricated to have a thickness of the order of a few hundreds nanometers to minimize IR loss. Yttrium-doped barium zirconate (BYZ), a proton conductor, was used as the electrolyte. We deposited a 350-nm-thick Pt (anode) layer on a porous substrate by sputter deposition. We also deposited a 1-${\mu}m$-thick BYZ layer on the Pt anode using pulsed laser deposition (PLD). Finally, we deposited a 200-nm-thick Pt (cathode) layer on the BYZ electrolyte by sputter deposition. The open circuit voltage (OCV) is 0.806 V, and the maximum power density is 11.9 mW/$cm^2$ at $350^{\circ}C$. Even though a fully dense electrolyte is deposited via PLD, a cross-sectional transmission electron microscopy (TEM) image reveals many voids and defects.

• Journal of Electrochemical Science and Technology
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• v.14 no.1
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• pp.85-95
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• 2023

In recent years, solid-state Li metal batteries (SSLBs) have attracted significant attention as the next-generation batteries with high energy and power densities. However, uncontrolled dendrite growth and the resulting pulverization of Li during repeated plating/stripping processes must be addressed for practical applications. Herein, we report a plastic-crystal-based polymer/ceramic composite solid electrolyte (PCCE) to resolve these issues. To fabricate the one-side ceramic-incorporated PCCE (CI-PCCE) film, a mixed precursor solution comprising plastic-crystal-based polymer (succinonitrile, SN) with garnet-structured ceramic (Li₇La₃Zr₂O₁₂, LLZO) particles was infused into a thin cellulose membrane, which was used as a mechanical framework, and subsequently solidified by using UV-irradiation. The CI-PCCE exhibited good flexibility and a high room-temperature ionic conductivity of over 10^-3 S cm^-1. The Li symmetric cell assembled with CI-PCCE provided enhanced durability against Li dendrite penetration through the solid electrolyte (SE) layer than those with LLZO-free PCCEs and exhibited long-term cycling stability (over 200 h) for Li plating/stripping. The enhanced Li⁺ transference number and lower interfacial resistance of CI-PCCE indicate that the ceramic-polymer composite layer in contact with the Li anode enabled the uniform distribution of Li⁺ flux at the interface between the Li metal and CI-PCCE, thereby promoting uniform Li plating/stripping. Consequently, the Li//LiFePO₄ (LFP) full cell constructed with CI-PCCE demonstrated superior rate capability (~120 mAh g^-1 at 2 C) and stable cycle performance (80% after 100 cycles) than those with ceramic-free PCCE.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.99-99
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• 2013

In this talk, I will present two research works in progress, which are: i) mapping of piezoelectric polarization and associated charge density distribution in the heteroepitaxial InGaN/GaN multi-quantum well (MQW) structure of a light emitting diode (LED) by using inline electron holography and ii) in-situ observation of the polarization switching process of an ferroelectric Pb(Zr1-x,Tix)O3 (PZT) thin film capacitor under an applied electric field in transmission electron microscope (TEM). In the first part, I will show that strain as well as total charge density distributions can be mapped quantitatively across all the functional layers constituting a LED, including n-type GaN, InGaN/GaN MQWs, and p-type GaN with sub-nm spatial resolution (~0.8 nm) by using inline electron holography. The experimentally obtained strain maps were verified by comparison with finite element method simulations and confirmed that not only InGaN QWs (2.5 nm in thickness) but also GaN QBs (10 nm in thickness) in the MQW structure are strained complementary to accommodate the lattice misfit strain. Because of this complementary strain of GaN QBs, the strain gradient and also (piezoelectric) polarization gradient across the MQW changes more steeply than expected, resulting in more polarization charge density at the MQW interfaces than the typically expected value from the spontaneous polarization mismatch alone. By quantitative and comparative analysis of the total charge density map with the polarization charge map, we can clarify what extent of the polarization charges are compensated by the electrons supplied from the n-doped GaN QBs. Comparison with the simulated energy band diagrams with various screening parameters show that only 60% of the net polarization charges are compensated by the electrons from the GaN QBs, which results in the internal field of ~2.0 MV cm-1 across each pair of GaN/InGaN of the MQW structure. In the second part of my talk, I will present in-situ observations of the polarization switching process of a planar Ni/PZT/SrRuO3 capacitor using TEM. We observed the preferential, but asymmetric, nucleation and forward growth of switched c-domains at the PZT/electrode interfaces arising from the built-in electric field beneath each interface. The subsequent sideways growth was inhibited by the depolarization field due to the imperfect charge compensation at the counter electrode and preexisting a-domain walls, leading to asymmetric switching. It was found that the preexisting a-domains split into fine a- and c-domains constituting a $90^{\circ}$ stripe domain pattern during the $180^{\circ}$ polarization switching process, revealing that these domains also actively participated in the out-of-plane polarization switching. The real-time observations uncovered the origin of the switching asymmetry and further clarified the importance of charged domain walls and the interfaces with electrodes in the ferroelectric switching processes.